Datasheet IRF530 (On Semiconductor) - 5
| Hersteller | On Semiconductor |
| Beschreibung | TMOS E−FET Power Field Effect. Transistor N−Channel Enhancement−Mode Silicon Gate |
| Seiten / Seite | 7 / 5 — IRF530. Figure 8. Gate−To−Source and Drain−To−Source. Figure 9. Resistive … |
| Dateiformat / Größe | PDF / 192 Kb |
| Dokumentensprache | Englisch |
IRF530. Figure 8. Gate−To−Source and Drain−To−Source. Figure 9. Resistive Switching Time. Voltage versus Total Charge
Textversion des Dokuments
IRF530
10 80 V 100 TS) DS TJ = 25°C 9 QT 72 (VOL , DRAIN−T ID = 8 A 8 V V GS 64 DD = 36 V V t TAGE GS = 10 V r 7 Q1 Q2 56 O−SOURCE td(off) VOL 6 48 (ns) tf 5 40 10 td(on) 4 32 VOL t, TIME 3 24 TAGE TE−TO−SOURCE 2 T 16 , GA J = 25°C (VOL ID = 14 A V GS 1 V Q3 DS 8 TS) 0 0 1 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 1 10 10 QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time Voltage versus Total Charge Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS
14 VGS = 0 V 12 TJ = 25°C 10 (AMPS) 8 6 4 , SOURCE CURRENT IS 2 00.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance The Forward Biased Safe Operating Area curves define dissipated in the transistor while in avalanche must be less the maximum simultaneous drain−to−source voltage and than the rated limit and adjusted for operating conditions drain current that a transistor can handle safely when it is differing from those specified. Although industry practice is forward biased. Curves are based upon maximum peak to rate in terms of energy, avalanche energy capability is not junction temperature and a case temperature (TC) of 25°C. a constant. The energy rating decreases non−linearly with Peak repetitive pulsed power limits are determined by using an increase of peak current in avalanche and peak junction the thermal response data in conjunction with the temperature. procedures discussed in AN569, “Transient Thermal Although many E−FETs can withstand the stress of Resistance−General Data and Its Use.” drain−to−source avalanche at currents up to rated pulsed Switching between the off−state and the on−state may current (IDM), the energy rating is specified at rated traverse any load line provided neither rated peak current continuous current (ID), in accordance with industry custom. (IDM) nor rated voltage (VDSS) is exceeded and the The energy rating must be derated for temperature as transition time (tr,tf) do not exceed 10 μs. In addition the shown in the accompanying graph (Figure 12). Maximum total power averaged over a complete switching cycle must energy at currents below rated continuous ID can safely be not exceed (TJ(MAX) − TC)/(RθJC). assumed to equal the values indicated. A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For
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10 80 V 100 TS) DS TJ = 25°C 9 QT 72 (VOL , DRAIN−T ID = 8 A 8 V V GS 64 DD = 36 V V t TAGE GS = 10 V r 7 Q1 Q2 56 O−SOURCE td(off) VOL 6 48 (ns) tf 5 40 10 td(on) 4 32 VOL t, TIME 3 24 TAGE TE−TO−SOURCE 2 T 16 , GA J = 25°C (VOL ID = 14 A V GS 1 V Q3 DS 8 TS) 0 0 1 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 1 10 10 QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time Voltage versus Total Charge Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS
14 VGS = 0 V 12 TJ = 25°C 10 (AMPS) 8 6 4 , SOURCE CURRENT IS 2 00.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance The Forward Biased Safe Operating Area curves define dissipated in the transistor while in avalanche must be less the maximum simultaneous drain−to−source voltage and than the rated limit and adjusted for operating conditions drain current that a transistor can handle safely when it is differing from those specified. Although industry practice is forward biased. Curves are based upon maximum peak to rate in terms of energy, avalanche energy capability is not junction temperature and a case temperature (TC) of 25°C. a constant. The energy rating decreases non−linearly with Peak repetitive pulsed power limits are determined by using an increase of peak current in avalanche and peak junction the thermal response data in conjunction with the temperature. procedures discussed in AN569, “Transient Thermal Although many E−FETs can withstand the stress of Resistance−General Data and Its Use.” drain−to−source avalanche at currents up to rated pulsed Switching between the off−state and the on−state may current (IDM), the energy rating is specified at rated traverse any load line provided neither rated peak current continuous current (ID), in accordance with industry custom. (IDM) nor rated voltage (VDSS) is exceeded and the The energy rating must be derated for temperature as transition time (tr,tf) do not exceed 10 μs. In addition the shown in the accompanying graph (Figure 12). Maximum total power averaged over a complete switching cycle must energy at currents below rated continuous ID can safely be not exceed (TJ(MAX) − TC)/(RθJC). assumed to equal the values indicated. A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For
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