Datasheet IRF530 (On Semiconductor) - 4

IRF530 POWER MOSFET SWITCHING
The capacitance (C Switching behavior is most easily modeled and predicted iss) is read from the capacitance curve at a voltage corresponding to the off−state condition when by recognizing that the power MOSFET is charge calculating t controlled. The lengths of various switching intervals ( d(on) and is read at a voltage corresponding to Δt) the on−state when calculating t are determined by how fast the FET input capacitance can d(off). be charged by current from the generator. At high switching speeds, parasitic circuit elements The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET calculating rise and fall because drain−gate capacitance source lead, inside the package and in the circuit wiring varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths, charge data is used. In most cases, a satisfactory estimate produces a voltage at the source which reduces the gate of average input current (IG(AV)) can be made from a drive current. The voltage is determined by Ldi/dt, but since rudimentary analysis of the drive circuit so that di/dt is a function of drain current, the mathematical solution t = Q/I is complex. The MOSFET output capacitance also G(AV) complicates the mathematics. And finally, MOSFETs have During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified. times may be approximated by the following: The resistive switching time variation versus gate tr = Q2 x RG/(VGG − VGSP) resistance (Figure 9) shows how typical switching t performance is affected by the parasitic circuit elements. If f = Q2 x RG/VGSP the parasitics were not present, the slope of the curves where would maintain a value of unity regardless of the switching VGG = the gate drive voltage, which varies from zero to VGG speed. The circuit used to obtain the data is constructed to R minimize common inductance in the drain and gate circuit G = the gate drive resistance loops and is believed readily achievable with board and Q2 and VGSP are read from the gate charge curve. mounted components. Most power electronic loads are During the turn−on and turn−off delay times, gate current is inductive; the data in the figure is taken with a resistive load, not constant. The simplest calculation uses appropriate which approximates an optimally snubbed inductive load. values from the capacitance curves in a standard equation Power MOSFETs may be safely operated into an inductive for voltage change in an RC network. The equations are: load; however, snubbing reduces switching losses. td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 2200 C V iss DS = 0 V VGS = 0 V TJ = 25°C 2000 1800 1600 (pF) 1400 ANCE 1200 Crss ACIT 1000 Ciss 800 C, CAP 600 400 Coss 200 Crss 010 5 0 5 10 15 20 25 VGS VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation http://onsemi.com 4