Datasheet PEMD12, PUMD12 (Nexperia) - 7

link to page 7
NXP Semiconductors PEMD12; PUMD12 NPN/PNP resistor-equipped transistors; R1 = 47 k , R2 = 47 k 7. Characteristics Table 8. Characteristics
Tamb = 25 C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit Per transistor; for the PNP transistor (TR2) with negative polarity
ICBO collector-base cut-off VCB = 50 V; IE = 0 A - - 100 nA current ICEO collector-emitter cut-off VCE = 30 V; IB = 0 A - - 1 A current VCE = 30 V; IB = 0 A; - - 5 A Tj = 150 C IEBO emitter-base cut-off VEB = 5 V; IC = 0 A - - 90 A current hFE DC current gain VCE = 5 V; IC = 5 mA 80 - - VCEsat collector-emitter IC = 10 mA; - - 150 mV saturation voltage IB = 0.5 mA VI(off) off-state input voltage VCE = 5 V; IC = 100 A - 1.2 0.8 V VI(on) on-state input voltage VCE = 0.3 V; IC = 2 mA 3 1.6 - V R1 bias resistor 1 (input) 33 47 61 k R2/R1 bias resistor ratio 0.8 1 1.2 Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz TR1 (NPN) - - 2.5 pF TR2 (PNP) - - 3 pF f [1] T transition frequency VCE = 5 V; IC = 10 mA; f = 100 MHz TR1 (NPN) - 230 - MHz TR2 (PNP) - 180 - MHz [1] Characteristics of built-in transistor PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 21 November 2011 6 of 16
Document Outline 1. Product profile 1.1 General description 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values 6. Thermal characteristics 7. Characteristics 8. Test information 8.1 Quality information 9. Package outline 10. Packing information 11. Soldering 12. Revision history 13. Legal information 13.1 Data sheet status 13.2 Definitions 13.3 Disclaimers 13.4 Trademarks 14. Contact information 15. Contents