Datasheet ADRV9009 (Analog Devices) - 5

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Data Sheet ADRV9009 SPECIFICATIONS
Electrical characteristics at VDDA1P31 = 1.3 V, VDDD1P3_DIG = 1.3 V, VDDA1P8_TX = 1.8 V, junction temperature (TJ) = full operating temperature range. LO frequency (fLO) = 1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer to the Typical Performance Characteristics section for input and output circuit path loss. The device configuration profile for the 75 MHz to 525 MHz frequency range is as follows: receiver = 50 MHz bandwidth (inphase quadrature (IQ) rate = 61.44 MHz), transmitter = 50 MHz transmitter large signal bandwidth and 100 MHz transmitter synthesis bandwidth (IQ rate = 122.88 MHz), observation receiver = 100 MHz bandwidth (IQ rate = 122.88 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Unless otherwise specified, the device configuration for all other frequency ranges is as follows: receiver = 200 MHz bandwidth (IQ rate = 245.76 MHz), transmitter = 200 MHz transmitter large signal bandwidth and 450 MHz transmitter synthesis bandwidth (IQ rate = 491.52 MHz), observation receiver = 450 MHz bandwidth (IQ rate = 491.52 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
TRANSMITTERS Center Frequency 75 6000 MHz Transmitter Synthesis 450 MHz Bandwidth Transmitter Large Signal 200 MHz Bandwidth Peak-to-Peak Gain 1.0 dB 450 MHz bandwidth, compensated by Deviation programmable finite impulse response (FIR) filter Gain Slope ±0.1 dB Any 20 MHz bandwidth span, compensated by programmable FIR filter Deviation from Linear Phase 1 Degrees 450 MHz bandwidth Transmitter Attenuation 0 32 dB Signal-to-noise ratio (SNR) maintained Power Control Range for attenuation between 0 dB and 20 dB Transmitter Attenuation 0.05 dB Power Control Resolution Transmitter Attenuation INL 0.1 dB For any 4 dB step Integral Nonlinearity Transmitter Attenuation DNL 0.04 dB Monotonic Differential Nonlinearity Transmitter Attenuation See Figure 4 Serial Peripheral Interface 2 (SPI 2) Timing Time from CS Going High tSCH 19.5 24 ns to Change in Transmitter Attenuation Time Between Consecutive tACH 6.5 8.1 ns A large change in attenuation can be Microattenuation Steps broken up into a series of smaller attenuation changes Time Required to Reach tDCH 800 ns Time required to complete the change Final Attenuation Value in attenuation from start attenuation to final attenuation value Maximum Attenuation −1.0 +0.5 dB Overshoot During Transition Change in Attenuation per 0.5 dB Microstep Maximum Attenuation 32 dB Change when CS Goes High Rev. B | Page 5 of 127 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Receiver Input Impedance Terminology Theory of Operation Transmitter Receiver Observation Receiver Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9009-W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide