Datasheet ADRV9009 (Analog Devices)

Integrated Dual RF Transmitter, Receiver, and Observation Receiver Data Sheet ADRV9009 FEATURES
In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing
Dual transmitters Dual receivers
significant flexibility in setting system level gain dynamically.
Dual input shared observation receiver
The received signals are digitized with a set of four high dynamic
Maximum receiver bandwidth: 200 MHz
range, continuous time Σ-Δ ADCs that provide inherent
Maximum tunable transmitter synthesis bandwidth:
antialiasing. The combination of the direct conversion
450 MHz
architecture, which does not suffer from out of band image
Maximum observation receiver bandwidth: 450 MHz
mixing, and the lack of aliasing, relaxes the requirements of the
Fully integrated fractional-N RF synthesizers
RF filters when compared to traditional intermediate frequency
Fully integrated clock synthesizer
(IF) receivers.
Multichip phase synchronization for RF LO and baseband
The transmitters use an innovative direct conversion
clocks
modulator that achieves high modulation accuracy with
JESD204B datapath interface
exceptionally low noise.
Tuning range (center frequency): 75 MHz to 6000 MHz
The observation receiver path consists of a wide bandwidth,
APPLICATIONS
direct conversion receiver with state-of-the-art dynamic range.
3G, 4G, and 5G TDD macrocell base stations
The fully integrated phase-locked loop (PLL) provides high
TDD active antenna systems
performance, low power, fractional-N RF frequency synthesis
Massive multiple input, multiple output (MIMO)
for the transmitter (Tx) and receiver (Rx) signal paths. An
Phased array radar
additional synthesizer generates the clocks needed for the
Electronic warfare
converters, digital circuits, and the serial interface. A multichip
Military communications
synchronization mechanism synchronizes the phase of the RF
Portable test equipment
local oscillator (LO) and baseband clocks between multiple
GENERAL DESCRIPTION
ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All The ADRV9009 is a highly integrated, radio frequency (RF), agile voltage controlled oscillators (VCOs) and loop filter transceiver offering dual transmitters and receivers, integrated components are integrated. synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low The high speed JESD204B interface supports up to 12.288 Gbps power consumption demanded by 3G, 4G, and 5G macro cell lane rates, resulting in two lanes per transmitter and a single time division duplex (TDD) base station applications. lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus The receive path consists of two independent, wide bandwidth, reducing the total number of high speed data interface lanes to direct conversion receivers with state-of-the-art dynamic range. one. Both fixed and floating point data formats are supported. The device also supports a wide bandwidth, time shared The floating point format allows internal AGC to be invisible to observation path receiver (ORx) for use in TDD applications. the demodulator device. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error The core of the ADRV9009 can be powered directly from 1.3 V correction (QEC), and digital filtering, thus eliminating the need regulators and 1.8 V regulators, and is controlled via a standard for these functions in the digital baseband. Several auxiliary 4-wire serial port. Comprehensive power-down modes are functions, such as analog-to-digital converters (ADCs), digital-to- included to minimize power consumption in normal use. The analog converters (DACs), and general-purpose inputs/outputs ADRV9009 is packaged in a 12 mm × 12 mm, 196-ball chip (GPIOs) for the power amplifier (PA), and RF front-end scale ball grid array (CSP_BGA). control are also integrated.
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Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Receiver Input Impedance Terminology Theory of Operation Transmitter Receiver Observation Receiver Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9009-W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide