Datasheet ADRV9009 (Analog Devices) - 10

ADRV9009 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LO SYNTHESIZER LO Frequency Step 2.3 Hz 1.5 GHz to 2.8 GHz, 76.8 MHz phase frequency detector (PFD) frequency LO Spur −85 dBc Excludes integer boundary spurs Integrated Phase Noise 2 kHz to 18 MHz 75 MHz LO 0.014 °rms Narrow PLL loop bandwidth (50 kHz) 1900 MHz LO 0.2 °rms Narrow PLL loop bandwidth (50 kHz) 3800 MHz LO 0.36 °rms Wide PLL loop bandwidth (300 kHz) 5900 MHz LO 0.54 °rms Wide PLL loop bandwidth (300 kHz) Spot Phase Noise 75 MHz LO Narrow PLL loop bandwidth 10 kHz Offset −126.5 dBc/Hz 100 kHz Offset −132.8 dBc/Hz 1 MHz Offset −150.1 dBc/Hz 10 MHz Offset −150.7 dBc/Hz 1900 MHz LO Narrow PLL loop bandwidth 100 kHz Offset −100 dBc/Hz 200 kHz Offset −115 dBc/Hz 400 kHz Offset −120 dBc/Hz 600 kHz Offset −129 dBc/Hz 800 kHz Offset −132 dBc/Hz 1.2 MHz Offset −135 dBc/Hz 1.8 MHz Offset −140 dBc/Hz 6 MHz Offset −150 dBc/Hz 10 MHz Offset −153 dBc/Hz 3800 MHz LO Wide PLL loop bandwidth 100 kHz Offset −104 dBc/Hz 1.2 MHz Offset −125 dBc/Hz 10 MHz Offset −145 dBc/Hz 5900 MHz LO Wide PLL loop bandwidth 100 kHz Offset −99 dBc/Hz 1.2 MHz Offset −119.7 dBc/Hz 10 MHz Offset −135.4 dBc/Hz LO PHASE SYNCHRONIZATION Phase Deviation 1.6 ps/°C Change in LO delay per temperature change EXTERNAL LO INPUT Input Frequency fEXTLO 150 8000 MHz Input frequency must be 2 × the desired LO frequency Input Signal Power 0 12 dBm 50 Ω matching at the source 3 dBm fEXTLO ≤ 2 GHz, add 0.5 dBm/GHz above 2 GHz 6 dBm fEXTLO = 8 GHz External LO Input Signal To ensure adequate QEC Differential Phase Error 3.6 ps Amplitude Error 1 dB Duty Cycle Error 2 % Even Order Harmonics −50 dBc CLOCK SYNTHESIZER Integrated Phase Noise 1 kHz to 100 MHz 1966.08 MHz LO 0.4 °rms PLL optimized for close in phase noise Rev. B | Page 10 of 127 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Receiver Input Impedance Terminology Theory of Operation Transmitter Receiver Observation Receiver Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9009-W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide