Datasheet AD9234 (Analog Devices) - 3

Data Sheet AD9234 REVISION HISTORY 1/2018—Rev. A to Rev. B 3/2015—Rev. 0 to Rev. A
Changes to Features Section .. 1 Added AD9234-500 ... Universal Added tACCESS Parameter, Table 5 ... 9 Changes to Features Section .. 1 Change to Junction Temperature Range Parameter, Table 6 .. 11 Changes to Table 1 .. 5 Changes to Figure 38 and Figure 39 ... 19 Changes to Table 2 .. 6 Added Deterministic Latency Section, Subclass 0 Operation Changes to Table 4 .. 9 Section, Subclass 1 Operation Section, Deterministic Latency Changes to Table 6, Thermal Characteristics Section, and Requirements Section, Setting Deterministic Latency Table 7 ... 11 Registers Section, and Figure 103; Renumbered Sequentially .. 46 Change to Pin 58, Pin 59 Description Column, Table 8 .. 15 Added Figure 104 and Figure 105 ... 47 Added AD9234-500 Section and Figure 29 to Figure 51 ... 18 Changes to Multichip Synchronization Section .. 48 Changes to Figure 63 Caption and Figure 64 Caption, Analog Input Added Normal Mode Section and Timestamp Mode Section ... 48 Controls and SFDR Optimization Section, and Figure 66 ... 25 Moved Figure 106 ... 48 Changes to Figure 70 and Figure 71 ... 26 Added Figure 107 ... 49 Changes to Voltage Reference Section .. 27 Added SYSREF± Input Section, SYSREF± Control Features Changes to Figure 79 .. 28 Section, Figure 108, Figure 109, Figure 110, Figure 111 ... 50 Changes to Figure 80 .. 29 Added Figure 112 and Figure 113 ... 51 Changes to DDC General Description Section .. 34 Changes to SYSREF± Setup/Hold Window Monitor Section ... 52 Changes to Figure 91 .. 38 Added Figure 114 ... 52 Added Example 2: Full Bandwidth Mode at 500 MSPS Section... 44 Added Figure 115 ... 53 Added Test Modes Section and Table 15 ... 50 Added Latency Section, End to End Total Latency Section, Added Table 16 and Table 17 ... 51 Table 15, Example Latency Calculation Section, Table 16, Added Table 18 and Table 19 ... 52 and Table 17; Renumbered Sequentially ... 54 Changes to Table 22 .. 55 Changes to ADC Test Modes Section and Table 18 ... 55 Changes to Power Supply Recommendations Section and Add Figure 116 .. 55 Figure 106 ... 65 Changes to Transport Layer Sample Test Mode Section, Changes to Ordering Guide ... 66 Interface Test Mode Section, and Table 19 ... 56 Moved Data Link Layer Test Modes Section .. 56
8/2014—Revision 0: Initial Version
Added Reg Addr (Hex) 0x122, Table 25... 62 Changes to Reg Addr (Hex) 0x56F, Table 25 ... 67 Updated Outline Dimensions .. 72 Changes to Ordering Guide ... 72 Rev. B | Page 3 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AD9234-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTER (DDC) DDC GENERAL DESCRIPTION HALF-BAND FILTER DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode at 1 GSPS Example 2: Full Bandwidth Mode at 500 MSPS Example 3: ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYSREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATION TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE