Datasheet AD9234 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter |
| Seiten / Seite | 72 / 2 — AD9234. Data Sheet. TABLE OF CONTENTS |
| Revision | B |
| Dateiformat / Größe | PDF / 1.7 Mb |
| Dokumentensprache | Englisch |
AD9234. Data Sheet. TABLE OF CONTENTS
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AD9234 Data Sheet TABLE OF CONTENTS
Features .. 1 DDC Complex to Real Conversion ... 36 Applications ... 1 Digital Outputs ... 37 Functional Block Diagram .. 1 Introduction to the JESD204B Interface ... 37 Product Highlights ... 1 JESD204B Overview .. 37 Revision History ... 3 Functional Overview ... 38 General Description ... 4 JESD204B Link Establishment ... 39 Specifications ... 5 Physical Layer (Driver) Outputs .. 41 DC Specifications ... 5 Configuring the JESD204B Link .. 43 AC Specifications .. 6 Deterministic Latency .. 46 Digital Specifications ... 8 Subclass 0 Operation .. 46 Switching Specifications .. 9 Subclass 1 Operation .. 46 Timing Specifications .. 9 Multichip Synchronization .. 48 Absolute Maximum Ratings .. 11 Normal Mode .. 48 Thermal Characteristics .. 11 Timestamp Mode ... 48 ESD Caution .. 11 SYSREF± Input ... 50 Pin Configuration and Function Descriptions ... 12 SYSREF± Setup/Hold Window Monitor ... 52 Typical Performance Characteristics ... 14 Latency ... 54 AD9234-1000 .. 14 End to End Total Latency .. 54 AD9234-500 .. 18 Example Latency Calculation ... 54 Equivalent Circuits ... 22 Test Modes ... 55 Theory of Operation .. 24 ADC Test Modes .. 55 ADC Architecture .. 24 JESD204B Block Test Modes .. 56 Analog Input Considerations .. 24 Serial Port Interface .. 58 Voltage Reference ... 27 Configuration Using the SPI ... 58 Clock Input Considerations .. 28 Hardware Interface ... 58 Clock Jitter Considerations ... 29 SPI Accessible Features .. 58 Power-Down/Standby Mode... 29 Memory Map .. 59 Temperature Diode .. 29 Reading the Memory Map Register Table ... 59 ADC Overrange and Fast Detect .. 30 Memory Map Register Table ... 60 ADC Overrange .. 30 Applications Information .. 71 Fast Threshold Detection (FD_A and FD_B) .. 30 Power Supply Recommendations ... 71 Signal Monitor .. 31 Exposed Pad Thermal Heat Slug Recommendations .. 71 Digital Downconverter (DDC) ... 34 AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) .. 71 DDC General Description .. 34 Outline Dimensions ... 72 Half-Band Filter .. 35 Ordering Guide .. 72 DDC Gain Stage ... 36 Rev. B | Page 2 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AD9234-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTER (DDC) DDC GENERAL DESCRIPTION HALF-BAND FILTER DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode at 1 GSPS Example 2: Full Bandwidth Mode at 500 MSPS Example 3: ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYSREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATION TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE
AD9234 Data Sheet TABLE OF CONTENTS
Features .. 1 DDC Complex to Real Conversion ... 36 Applications ... 1 Digital Outputs ... 37 Functional Block Diagram .. 1 Introduction to the JESD204B Interface ... 37 Product Highlights ... 1 JESD204B Overview .. 37 Revision History ... 3 Functional Overview ... 38 General Description ... 4 JESD204B Link Establishment ... 39 Specifications ... 5 Physical Layer (Driver) Outputs .. 41 DC Specifications ... 5 Configuring the JESD204B Link .. 43 AC Specifications .. 6 Deterministic Latency .. 46 Digital Specifications ... 8 Subclass 0 Operation .. 46 Switching Specifications .. 9 Subclass 1 Operation .. 46 Timing Specifications .. 9 Multichip Synchronization .. 48 Absolute Maximum Ratings .. 11 Normal Mode .. 48 Thermal Characteristics .. 11 Timestamp Mode ... 48 ESD Caution .. 11 SYSREF± Input ... 50 Pin Configuration and Function Descriptions ... 12 SYSREF± Setup/Hold Window Monitor ... 52 Typical Performance Characteristics ... 14 Latency ... 54 AD9234-1000 .. 14 End to End Total Latency .. 54 AD9234-500 .. 18 Example Latency Calculation ... 54 Equivalent Circuits ... 22 Test Modes ... 55 Theory of Operation .. 24 ADC Test Modes .. 55 ADC Architecture .. 24 JESD204B Block Test Modes .. 56 Analog Input Considerations .. 24 Serial Port Interface .. 58 Voltage Reference ... 27 Configuration Using the SPI ... 58 Clock Input Considerations .. 28 Hardware Interface ... 58 Clock Jitter Considerations ... 29 SPI Accessible Features .. 58 Power-Down/Standby Mode... 29 Memory Map .. 59 Temperature Diode .. 29 Reading the Memory Map Register Table ... 59 ADC Overrange and Fast Detect .. 30 Memory Map Register Table ... 60 ADC Overrange .. 30 Applications Information .. 71 Fast Threshold Detection (FD_A and FD_B) .. 30 Power Supply Recommendations ... 71 Signal Monitor .. 31 Exposed Pad Thermal Heat Slug Recommendations .. 71 Digital Downconverter (DDC) ... 34 AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) .. 71 DDC General Description .. 34 Outline Dimensions ... 72 Half-Band Filter .. 35 Ordering Guide .. 72 DDC Gain Stage ... 36 Rev. B | Page 2 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AD9234-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTER (DDC) DDC GENERAL DESCRIPTION HALF-BAND FILTER DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode at 1 GSPS Example 2: Full Bandwidth Mode at 500 MSPS Example 3: ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYSREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATION TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE