Datasheet AD9234 (Analog Devices) - 5

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Data Sheet AD9234 SPECIFICATIONS DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 1. AD9234-500 AD9234-1000 Parameter Temperature Min Typ Max Min Typ Max Unit
RESOLUTION Full 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −0.22 0 +0.20 −0.22 0 +0.20 % FSR Offset Matching Full 0 +0.19 0 +0.19 % FSR Gain Error Full −13.8 −5.1 +3.6 0 % FSR Gain Matching Full −3.9 +1 +5.9 1 +4.8 % FSR Differential Nonlinearity (DNL) Full −0.3 +0.3 −0.3 ±0.16 +0.3 LSB Integral Nonlinearity (INL) Full −0.8 +1.1 −1.2 ±35 +1.4 LSB TEMPERATURE DRIFT Offset Error 25°C ±2.6 ±6 ppm/°C Gain Error 25°C ±36 ±36 ppm/°C INTERNAL VOLTAGE REFERENCE Voltage Full 1.0 1.0 V INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.74 1.02 LSB rms ANALOG INPUTS Differential Input Voltage Range Full 1.63 1.34 V p-p Common-Mode Voltage (VCM) 25°C 2.05 2.05 V Differential Input Capacitance1 25°C 1.5 1.5 pF Analog Input Full Power Bandwidth 25°C 2 2 GHz POWER SUPPLY AVDD1 Full 1.22 1.25 1.28 1.22 1.25 1.28 V AVDD2 Full 2.44 2.50 2.56 2.44 2.50 2.56 V AVDD3 Full 3.2 3.3 3.4 3.2 3.3 3.4 V AVDD1_SR Full 1.22 1.25 1.28 1.22 1.25 1.28 V DVDD Full 1.22 1.25 1.28 1.22 1.25 1.28 V DRVDD Full 1.22 1.25 1.28 1.22 1.25 1.28 V SPIVDD Full 1.7 1.8 3.4 1.7 1.8 3.4 V IAVDD1 Full 430 480 675 740 mA IAVDD2 Full 380 430 525 590 mA IAVDD3 Full 65 75 75 91 mA IAVDD1_SR Full 15 18 16 18 mA I 2 DVDD Full 140 152 230 236 mA I 1 DRVDD Full 190 246 205 225 mA IDRVDD (L = 2 mode) 25°C 140 N/A3 mA ISPIVDD Full 5 6 5 6 mA Rev. B | Page 5 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AD9234-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTER (DDC) DDC GENERAL DESCRIPTION HALF-BAND FILTER DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode at 1 GSPS Example 2: Full Bandwidth Mode at 500 MSPS Example 3: ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYSREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATION TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE