AD7703* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017COMPARABLE PARTSDESIGN RESOURCES View a parametric search of comparable parts. • AD7703 Material Declaration • PCN-PDN Information DOCUMENTATION • Quality And Reliability Application Notes • Symbols and Footprints • AN-349: Keys to Longer Life for CMOS • AN-368: Evaluation Board for the AD7701/AD7703 Sigma- DISCUSSIONS Delta ADCs View all AD7703 EngineerZone Discussions. • AN-375: ADM2xxL Family for RS-232 Communications • AN-607: Selecting a Low Bandwidth (<15 kSPS) Sigma- SAMPLE AND BUY Delta ADC Visit the product page to see pricing options. Data Sheet • AD7703: LC2MOS 20-Bit Sigma-Delta ADC Data Sheet TECHNICAL SUPPORT Submit a technical question or find your regional support TOOLS AND SIMULATIONS number. • Sigma-Delta ADC Tutorial DOCUMENT FEEDBACKREFERENCE MATERIALS Submit feedback for this data sheet. Technical Articles • Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter • MS-2210: Designing Power Supplies for High Speed ADC This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span PIN CONFIGURATION DIP, CERDIP, SOIC PIN FUNCTION DESCRIPTIONS GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7703 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES ACCURACY AUTOCALIBRATION Initiating Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS POWER SUPPLIES AND GROUNDING SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS REVISION HISTORY