Datasheet AD7703 (Analog Devices) - 10

AD7703 Table II. Resonator Loading Capacitors
low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper-stabilized techniques in
Resonators C1 (pF) C2 (pF)
its input stage. To ensure excellent performance over time and Ceramic temperature, the AD7703 uses digital calibration techniques 200 kHz 330 470 that minimize offset and gain error to typically ±4 LSB. 455 kHz 100 100 1.0 MHz 50 50
AUTOCALIBRATION
2.0 MHz 20 20 The AD7703 offers both self-calibration and system-calibration facilities. For calibration to occur, the on-chip microcontroller Crystal must record the modulator output for two different input condi- 2.000 MHz 30 30 tions. These are the zero-scale and full-scale points. In Unipolar 3.579 MHz 20 20 self-calibration mode, the zero-scale point is V 4.096 MHz None None AGND and the full-scale point is VREF. With these readings, the microcontroller can calculate the gain slope for the input to output transfer The input sampling frequency, output data rate, filter character- function of the converter. In Unipolar mode, the slope factor is istics, and calibration time are all directly related to the master determined by dividing the span between zero and full scale by clock frequency, fCLKIN, by the ratios given in the Specification 220. In Bipolar mode, it is determined by dividing the span by table under Dynamic Performance. Therefore, the first step in 219 since the inputs applied represent only half the total codes. system design with the AD7703 is to select a master clock fre- In both Unipolar and Bipolar modes, the slope factor is saved quency suitable for the bandwidth and output data rate required and used to calculate the binary output code when an analog by the application. input is applied to the device. Table IV gives the output code size after calibration.
ANALOG INPUT RANGES
System calibration allows the AD7703 to compensate for system The AD7703 performs conversion relative to an externally gain and offset errors. A typical circuit where this might be used supplied reference voltage that allows easy interfacing to ratio- is shown in Figure 12. metric systems. In addition, either unipolar or bipolar input voltage ranges may be selected using the BP/UP input. With System calibration performs the same slope factor calculations BP/UP tied low, the input range is unipolar and the span is as self-calibration but uses voltage values presented by the system (V to the A REF to VAGND), where VAGND is the voltage at the device AGND IN pin for the zero- and full-scale points. There are two pin. With BP/UP tied high, the input range is bipolar and the system calibration modes. span is 2VREF. In the Bipolar mode, both positive and negative The first mode offers system level calibration for system offset full scale are directly determined by VREF. This offers superior and system gain. This is a two step operation. The zero-scale tracking of positive and negative full scale and better midscale point must be presented to the converter first. It must be applied (bipolar zero) stability than bipolar schemes that simply scale to the converter before the calibration step is initiated and remain and offset the input range. stable until the step is complete. The DRDY output from the The digital output coding for the unipolar range is unipolar binary; device will signal when the step is complete by going low. After for the bipolar range it is offset binary. Bit weights for the Unipolar the zero-scale point is calibrated, the full-scale point is applied and Bipolar modes are shown in Table I. and the second calibration step is initiated. Again, the voltage must remain stable throughout the calibration step.
ACCURACY
The two step calibration mode offers another feature. After the S-D ADCs, like VFCs and other integrating ADCs, do not sequence has been completed, additional offset calibrations can be contain any source of nonmonotonicity and inherently offer performed by themselves to adjust the zero reference point to a no-missing-codes performance. new system zero reference value. This second system calibration The AD7703 achieves excellent linearity by the use of high mode uses an input voltage for the zero-scale calibration point quality, on-chip silicon dioxide capacitors, which have a very but uses the VREF value for the full-scale point.
SYSTEM SCLK REF HI SDATA ANALOG SIGNAL A A CAL IN MUX CONDITIONING IN MICRO- SC1 COMPUTER SYSTEM A0 A1 AD7703 SC2 REF LO
Figure 12. Typical Connections for System Calibration REV. E –9– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span PIN CONFIGURATION DIP, CERDIP, SOIC PIN FUNCTION DESCRIPTIONS GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7703 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES ACCURACY AUTOCALIBRATION Initiating Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS POWER SUPPLIES AND GROUNDING SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS REVISION HISTORY