Datasheet AD7703 (Analog Devices) - 4

AD7703 Parameter A/S Version2 B Version2 C Version2 Unit Test Conditions/Comments
POWER REQUIREMENTS DC Power Supply Currents8 Analog Positive Supply (AIDD) 2.7 2.7 2.7 mA max Typically 2 mA Digital Positive Supply (DIDD) 2 2 2 mA max Typically 1 mA Analog Negative Supply (AISS) 2.7 2.7 2.7 mA max Typically 2 mA Digital Negative Supply (DISS) 0.1 0.1 0.1 mA max Typically 0.03 mA Power Supply Rejection9 Positive Supplies 70 70 70 dB typ Negative Supplies 75 75 75 dB typ Power Dissipation Normal Operation 37 37 37 mW max SLEEP = Logic 1, Typically 25 mW Standby Operations10 SLEEP = Logic 0, A, B, C 20 20 20 µW max Typically 10 µW S 40 40 40 µW max NOTES 1 The AIN pin presents a very high impedance dynamic load that varies with clock frequency. A ceramic 1 nF capacitor from the AIN pin to AGND is necessary. Source resistance should be 750 or less. 2 Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C; S Version: –55°C to +125°C. 3 Applies after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges. 4 Total drift over the specified temperature range after calibration at power-up at 25 °C. This is guaranteed by design and/or characterization. Recalibration at any temperature will remove these errors. 5 In Unipolar mode, the offset can have a negative value (–VREF) such that the Unipolar mode can mimic Bipolar mode operation. 6 The specifications for input overrange and for input span apply additional constraints on the offset calibration range. 7 For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ± (VREF + 0.1). 8 All digital outputs unloaded. All digital inputs at 5 V CMOS levels. 9 Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter. 10 CLKIN is stopped. All digital inputs are grounded. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause (TA = 25°C, unless otherwise noted.) permanent damage to the device. This is a stress rating only; functional operation DVDD to AGND . –0.3 V to +6 V of the device at these or any other conditions above those listed in the DV operational sections of this specification is not implied. Exposure to absolute DD to AVDD . –0.3 V to +0.3 V DV maximum rating conditions for extended periods may affect device reliability. SS to AGND . +0.3 V to –6 V 2Transient currents of up to 100 mA will not cause SCR latch-up. AVDD to AGND . –0.3 V to +6 V AVSS to AGND . +0.3 V to –6 V
ORDERING GUIDE
AGND to DGND . –0.3 V to +0.3 V Digital Input Voltage to DGND . –0.3 V to DVDD + 0.3 V
Linearity
Analog Input Voltage to AGND . AVSS – 0.3 V to AVDD + 0.3 V
Temperature Error Package
Input Current to Any Pin Except Supplies2 . ± 10 mA
Model Range (% FSR) Options*
Operating Temperature Range Industrial (A, B, C Versions) . –40°C to +85°C AD7703AN –40°C to +85°C 0.003 N-20 Extended (S Version) . –55°C to +125°C AD7703BN –40°C to +85°C 0.0015 N-20 Storage Temperature Range . –65°C to +150°C AD7703CN –40°C to +85°C 0.0012 N-20 Lead Temperature (Soldering, 10 secs) . 300°C AD7703AR –40°C to +85°C 0.003 R-20 Power Dissipation (DIP Package) to 75°C . 450 mW AD7703BR –40°C to +85°C 0.0015 R-20 Derates above 75°C by . 10 mW/°C AD7703CR –40°C to +85°C 0.0012 R-20 Power Dissipation (SOIC Package) to 75°C . 250 mW AD7703AQ –40°C to +85°C 0.003 Q-20 Derates above 75°C by . 15 mW/°C AD7703BQ –40°C to +85°C 0.0015 Q-20 AD7703CQ –40°C to +85°C 0.0012 Q-20 AD7703SQ –55°C to +125°C 0.003 Q-20 *N = Plastic DIP; R = SOIC; Q = CERDIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7703 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. E –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span PIN CONFIGURATION DIP, CERDIP, SOIC PIN FUNCTION DESCRIPTIONS GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7703 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES ACCURACY AUTOCALIBRATION Initiating Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS POWER SUPPLIES AND GROUNDING SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS REVISION HISTORY