AD7722DOEtt1 51 6SDO Figure 5. Serial Mode Timing for Data Output Enable and Serial Data Output (TSI = Logic Low) t17t18DRDYt19t25CSt20t24t21RDtt232 2DB0–DB15VALID DATA Figure 6. Parallel Mode Read Timing t30CLKINt28 MINt28 MAXt31SYNC, RESETt26t27DVALt29DRDY Figure 7. SYNC and RESET Timing, Serial and Parallel Mode t36CLKINt34SYNC, RESETt35t37 UNI = 1t37 UNI = 08192 tDVALCLK8192 tCLK8192 tCLK8192 tCLK512 t512 t512 tCLKCLKCLKt38DRDY Figure 8. Calibration Timing, Serial and Parallel Mode REV. B –7– Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History