Datasheet AD7722 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| Seiten / Seite | 25 / 7 — AD7722. 64 CKLIN CYCLES. CLKIN. SCO. (CFMT = 0). 32 SCO CYCLES. FSO. … |
| Revision | C |
| Dateiformat / Größe | PDF / 478 Kb |
| Dokumentensprache | Englisch |
AD7722. 64 CKLIN CYCLES. CLKIN. SCO. (CFMT = 0). 32 SCO CYCLES. FSO. (SFMT = 0). VALID DATA FOR 16 SCO CYCLES
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AD7722 64 CKLIN CYCLES CLKIN SCO (CFMT = 0) 32 SCO CYCLES FSO (SFMT = 0) SCO VALID DATA FOR 16 SCO CYCLES ZERO FOR LAST 16 SCO CYCLES VALID
Figure 2a. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
64 CKLIN CYCLES CLKIN SCO (CFMT = 0) 32 SCO CYCLES FSO LOW FOR 16 SCO CYCLES (SFMT = 1) HIGH FOR LAST 16 SCO CYCLES SCO VALID DATA FOR 16 SCO CYCLES ZERO FOR LAST 16 SCO CYCLES VALID
Figure 2b. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
t t 5 4 t2 2.3V CLKIN 0.8V t3 t1 t8 t6 FSI t t 7 9 SCO t9 t10
Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output
CLKIN t1 FSI t10 SCO t11 t12 SFMT = LOGIC FSO LOW(0) t14 SDO D15 D14 D13 D1 D0 t13 SCO t12 t11 SFMT = LOGIC LOW FOR FSO D15–D0 HIGH(1) t13 SDO D15 D14 D13 D1 D0
Figure 4. Serial Mode Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (CFMT = Logic Low, TSI = DOE) –6– REV. B Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History
Figure 2a. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
64 CKLIN CYCLES CLKIN SCO (CFMT = 0) 32 SCO CYCLES FSO LOW FOR 16 SCO CYCLES (SFMT = 1) HIGH FOR LAST 16 SCO CYCLES SCO VALID DATA FOR 16 SCO CYCLES ZERO FOR LAST 16 SCO CYCLES VALID
Figure 2b. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
t t 5 4 t2 2.3V CLKIN 0.8V t3 t1 t8 t6 FSI t t 7 9 SCO t9 t10
Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output
CLKIN t1 FSI t10 SCO t11 t12 SFMT = LOGIC FSO LOW(0) t14 SDO D15 D14 D13 D1 D0 t13 SCO t12 t11 SFMT = LOGIC LOW FOR FSO D15–D0 HIGH(1) t13 SDO D15 D14 D13 D1 D0
Figure 4. Serial Mode Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (CFMT = Logic Low, TSI = DOE) –6– REV. B Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History