Datasheet AD7722 (Analog Devices) - 2

AD7722* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS
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Technical Articles
• Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
EVALUATION KITS
• MS-2210: Designing Power Supplies for High Speed ADC • AD7722 Evaluation Board • Part 1: Circuit Suggestions Using Features and Functionality of New Sigma-Delta ADCs
DOCUMENTATION
• Part 2: Circuit Suggestions Using Features and
Application Notes
Functionality of New Sigma-Delta ADCs • AN-202: An IC Amplifier User’s Guide to Decoupling, Grounding, and Making Things Go Right for a Change
DESIGN RESOURCES
• AN-283: Sigma-Delta ADCs and DACs • AD7722 Material Declaration • AN-311: How to Reliably Protect CMOS Circuits Against • PCN-PDN Information Power Supply Overvoltaging • Quality And Reliability • AN-388: Using Sigma-Delta Converters-Part 1 • Symbols and Footprints • AN-389: Using Sigma-Delta Converters-Part 2 • AN-397: Electrically Induced Damage to Standard Linear
DISCUSSIONS
Integrated Circuits: View all AD7722 EngineerZone Discussions.
Data Sheet
• AD7722: 16-Bit, 195 kSPS CMOS, Σ-Δ ADC Data Sheet
SAMPLE AND BUY
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TOOLS AND SIMULATIONS
• Sigma-Delta ADC Tutorial
TECHNICAL SUPPORT
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Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History