Datasheet AD7722 (Analog Devices) - 10

AD7722 PIN CONFIGURATION 44-Lead MQFP (S-44B) DD TSI/DB3 DOE/DB4 SFMT/DB5 FSI/DB6 SCO/DB7 DV SDO/DB8 FSO/DB9 DGND/DB10 DGND/DB11 DGND/DB12 44 43 42 41 40 39 38 37 36 35 34 DGND/DB2 1 33 DGND/DB13 PIN 1 DGND/DB1 2 IDENTIFIER 32 DGND/DB14 DGND/DB0 3 31 DGND/DB15 CFMT/DRDY 4 30 SYNC DVAL/RD 5 29 CS AD7722 DGND 6 TOP VIEW 28 DGND (Not to Scale) UNI 7 27 CAL P/S 8 26 AGND AGND 9 25 AGND AGND1 10 24 REF2 CLKIN 11 23 AVDD 12 13 14 15 16 17 18 19 20 21 22 (–) (+) DD DD1 IN IN XTAL AGND AV AGND V V RESET AGND AV AGND REF1 PARALLEL MODE PIN FUNCTION DESCRIPTIONS Mnemonic Pin No. Description
DVAL/RD 5 Read input is a level sensitive logic input. The RD logic level is sensed on the rising edge of CLKIN. This digital input can be used in conjunction with CS to read data from the device. The output data bus is enabled when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When RD is sensed high, the output data bits DB15–DB0 will be high impedance. CFMT/DRDY 4 Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the output data register. DRDY will return high upon completion of a read operation. If a read operation does not occur between output updates, DRDY will pulse high for two CLKIN cycles before the next output update. DRDY also indicates when conversion results are available after a SYNC or RESET sequence and when completing a self-calibration. DGND/DB15 31 Data Output Bit (MSB). DGND/DB14 32 Data Output Bit. DGND/DB13 33 Data Output Bit. DGND/DB12 34 Data Output Bit. DGND/DB11 35 Data Output Bit. DGND/DB10 36 Data Output Bit. FSO/DB9 37 Data Output Bit. SDO/DB8 38 Data Output Bit. SCO/DB7 40 Data Output Bit. FSI/DB6 41 Data Output Bit. SFMT/DB5 42 Data Output Bit. DOE/DB4 43 Data Output Bit. TSI/DB3 44 Data Output Bit. DGND/DB2 1 Data Output Bit. DGND/DB1 2 Data Output Bit. DGND/DB0 3 Data Output Bit (LSB). REV. B –9– Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History