Datasheet AD7176-2 (Analog Devices) - 10

Data Sheet AD7176-2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AIN4 1 24 AIN3 REF– 2 23 AIN2 REF+ 3 22 AIN1 REFOUT 4 21 AIN0 REGCAPA 5 20 GPIO1 AD7176-2 AVSS 6 19 GPIO0 TOP VIEW AVDD1 7 (Not to Scale) 18 REGCAPD 8 AVDD2 17 DGND XTAL1 9 16 IOVDD CLKIO/XTAL2 10 15 SYNC/ERROR DOUT/RDY 11 14 CS
004
DIN 12 13 SCLK
1037- 1 Figure 4. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 AIN4 Analog Input 4. Selectable through crosspoint multiplexer. 2 REF− Reference Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V. 3 REF+ Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+ can span from AVDD1 to AVSS + 1 V. The part functions with a reference from 1 V to AVDD1. 4 REFOUT Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. 5 REGCAPA Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor. 6 AVSS Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V. 7 AVDD1 Analog Supply Voltage 1. This voltage is 5 V ± 10% with respect to AVSS. 8 AVDD2 Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS. 9 XTAL1 Input 1 for Crystal. 10 CLKIO/XTAL2 Clock Input or Output (Based on the CLOCKSEL Bits in the ADCMODE Register)/Input 2 for Crystal. There are four options available: Internal oscillator—no output. Internal oscillator—output to CLKIO/XTAL2. Operates at IOVDD logic level. External clock—input to CLKIO/XTAL2. Input should be at IOVDD logic level. External crystal—connected between XTAL1 and CLKIO/XTAL2. 11 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is tristated. When CS is low, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. 12 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register address (RA) bits of the communications register identifying the appropriate register. Data is clocked in on the rising edge of SCLK. 13 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. 14 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. When CS is high, the DOUT/RDY output is tristated. Rev. D | Page 9 of 68 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7176-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs Pseudo Differential Inputs DRIVER AMPLIFIERS AD8475 AD8656 ADA4940-1/ADA4940-2 AD7176-2 REFERENCE External Reference Internal Reference AD7176-2 CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION (SYNC\/ERROR\) ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Pin DATA_STAT IOSTRENTGH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL MAP REGISTER 0 CHANNEL MAP REGISTER 1 CHANNEL MAP REGISTER 2 CHANNEL MAP REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 SETUP CONFIGURATION REGISTER 2 SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 FILTER CONFIGURATION REGISTER 2 FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 OFFSET REGISTER 2 OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 GAIN REGISTER 2 GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE