Datasheet AD9625 (Analog Devices) - 7

Data Sheet AD9625 SWITCHING SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = −1.0 dBFS, default SPI settings, unless otherwise noted.
Table 4. Parameter Test Conditions/Comments Temperature1 Min Typ Max Unit
CLOCK (CLK) Maximum Clock Rate Full 2600 MSPS Minimum Clock Rate Full 3302 MSPS Clock Pulse Width High Full 50 ± 5 % duty cycle Clock Pulse Width Low Full 50 ± 5 % duty cycle SYSREF (SYSREF±)3 Setup Time (tSU_SR) 25°C +200 ps Hold Time (tH_SR) 25°C −100 ps FAST DETECT OUTPUT (FD) Latency Full 82 Clock cycles OUTPUT PARAMETERS (SERDOUT[x]±) Rise Time 25°C 70 ps Fall Time 25°C 70 ps Pipeline Latency Eight lane mode 25°C 226 Clock cycles SYNCB± Falling Edge to First K.28 Characters 25°C 4 Multiframes CGS Phase K.28 Characters Duration 25°C 1 Multiframes Differential Termination Resistance 25°C 100 Ω APERTURE Delay Full 200 ps Uncertainty (Jitter) Full 80 fS rms Out-of-Range Recovery Time Full 2 Clock cycles 1 Full temperature range is −40°C to +85°C measured at the case (TC). 2 Must use a two-lane, generic output lane configuration for minimum sample rate. For more information, see the lane table in the JESD204B specification document. 3 SYSREF± setup and hold times are defined with respect to the rising SYSREF± edge and rising clock edge. Positive setup time leads the clock edge. Negative hold time also leads the clock edge.
TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit
SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK should be in a logic high state 10 ns tLOW Minimum period that SCLK should be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an 10 ns output relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns input relative to the SCLK rising edge Rev. B | Page 7 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE