Datasheet AD9625 (Analog Devices) - 6

AD9625 Data Sheet DIGITAL SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = −1.0 dBFS, default SPI settings, unless otherwise noted.
Table 3. Parameter Temperature1 Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Differential Input Voltage Full 500 1800 mV p-p Common-Mode Input Voltage Full 0.88 V Input Resistance (Differential) Full 40 kΩ Input Capacitance Full 1.5 pF SYSREF INPUTS (SYSREF+, SYSREF−) Differential Input Voltage Full 500 1800 mV p-p Common-Mode Input Voltage Full 0.88 V Input Resistance (Differential) Full 40 kΩ Input Capacitance Full 1.5 pF LOGIC INPUTS (SDIO, SCLK, CSB) Logic Compliance CMOS Voltage Logic 1 Full 0.8 × SPI_DVDDIO V Logic 0 Full 0.5 V Input Resistance Full 30 kΩ Input Capacitance Full 0.5 pF SYNCB+/SYNCB− INPUT Logic Compliance Full LVDS Input Voltage Differential Full 250 1200 mV p-p Common Mode Full 1.2 V Input Resistance (Differential) Full 100 Ω Input Capacitance Full 2.5 pF LOGIC OUTPUT (SDIO) Logic Compliance CMOS Voltage Logic 1 (IOH = 800 μA) Full 0.8 × SPI_VDDIO V Logic 0 (IOL = 50 μA) Full 0.3 V DIGITAL OUTPUTS (SERDOUT[x]±) Compliance Full CML Output Voltage Differential Full 360 700 800 mV p-p Offset Full DRVDD/2 mV p-p Differential Return Loss (RLDIFF)2 25°C 8 dB Common-Mode Return Loss (RLCM) 25°C 6 dB Differential Termination Impedance 25°C 100 Ω RESET (RSTB) Voltage Logic 1 Full 0.8 × DVDDIO V Logic 0 Full 0.5 V Input Resistance (Differential) Full 20 kΩ Input Capacitance Full 2.5 pF FAST DETECT (FD), PWDN, AND INTERRUPT (IRQ) Logic Compliance CMOS Voltage Logic 1 Full 0.8 × DVDDIO V Logic 0 Full 0.5 V Input Resistance (Differential) Full 20 kΩ Input Capacitance Full 2.5 pF 1 Full temperature range is −40°C to +85°C measured at the case (TC). 2 Differential and common-mode return loss measured from 100 MHz to 0.75 × baud rate. Rev. B | Page 6 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE