Datasheet AD9625 (Analog Devices)

12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter Data Sheet AD9625 FEATURES FUNCTIONAL BLOCK DIAGRAM 12-bit 2.5 GSPS ADC, no missing codes AVDD AGND DRVDD DRGND SFDR = 79 dBc, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS REFERENCE DIGITAL INTERFACE SFDR = 77 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS AND CONTROL SERDOUT[0]± SERDOUT[1]± SNR = 57.6 dBFS, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS VCM ACE SERDOUT[2]± SERDOUT[3]± D204B RF SNR = 57 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS VIN+ S E SERDOUT[4]± DDC ADC SERDOUT[5]± JE CORE f INT Noise spectral density = −149.5 dBFS/Hz at 2.5 GSPS S/8 OR fS/16 SERDOUT[6]± VIN– SERDOUT[7]± Differential analog input: 1.2 V p-p RBIAS_EXT CONTROL CMOS FD Differential clock input REGISTERS DIGITAL RSTB INPUT/ 3.2 GHz analog input bandwidth, full power OUTPUT IRQ High speed 6- or 8-lane JESD204B serial output at 2.6 GSPS SYSREF± CLOCK LVDS SYNCINB± MANAGEMENT DIGITAL Subclass 1: 6.5 Gbps at 2.6 GSPS CLK± INPUT/ OUTPUT DIVCLK± CMOS DIGITAL Two independent decimate by 8 or decimate by 16 filters INPUT/OUTPUT AD9625 with 10-bit NCOs Supply voltages: 1.3 V, 2.5 V
001
SDIO SCLK CSB
1814- 1
Serial port control
Figure 1.
Flexible digital output modes Built-in selectable digital test patterns Timestamp feature Conversion error rate < 10−15 APPLICATIONS Spectrum analyzers Military communications Radar High performance digital storage oscilloscopes Active jamming/antijamming Electronic surveillance and countermeasures GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD9625 is a 12-bit monolithic sampling analog-to-digital 1. High performance: exceptional SFDR in high sample rate converter (ADC) that operates at conversion rates of up to applications, direct RF sampling, and on-chip reference. 2.6 giga samples per second (GSPS). This product is designed 2. Flexible digital data output formats based on the JESD204B for sampling wide bandwidth analog signals up to the second specification. Nyquist zone. The combination of wide input bandwidth, high 3. Control path SPI interface port that supports various sampling rate, and excellent linearity of the AD9625 is ideally product features and functions, such as data formatting, suited for spectrum analyzers, data acquisition systems, and a gain, and offset calibration values. wide assortment of military electronics applications, such as radar and electronic countermeasures. The analog input, clock, and SYSREF± signals are differential inputs. The JESD204B-based high speed serialized output is configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The product is specified over the industrial temperature range of −40°C to +85°C, measured at the case.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE