Datasheet TLV9061, TLV9062, TLV9064 (Texas Instruments) - 10
| Hersteller | Texas Instruments |
| Beschreibung | 10-MHz, RRIO, CMOS Operational Amplifiers For Cost-Sensivite Systems |
| Seiten / Seite | 82 / 10 — TLV9061,. TLV9062,. TLV9064. www.ti.com. Pin Functions: TLV9064 … |
| Dateiformat / Größe | PDF / 5.9 Mb |
| Dokumentensprache | Englisch |
TLV9061,. TLV9062,. TLV9064. www.ti.com. Pin Functions: TLV9064 (continued). PIN. I/O. DESCRIPTION. SOIC,. NAME. WQFN. X2QFN. TSSOP
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TLV9061, TLV9062, TLV9064
SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
www.ti.com Pin Functions: TLV9064 (continued) PIN I/O DESCRIPTION SOIC, NAME WQFN X2QFN TSSOP
NC — 6, 7 — — No internal connection OUT1 1 15 14 O Output, channel 1 OUT2 7 5 6 O Output, channel 2 OUT3 8 8 7 O Output, channel 3 OUT4 14 14 13 O Output, channel 4 V– 11 11 10 I or — Negative (low) supply or ground (for single-supply operation) V+ 4 2 3 I Positive (high) supply 10 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated Product Folder Links: TLV9061 TLV9062 TLV9064 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Description (continued) 6 Device Comparison Table 7 Pin Configuration and Functions 8 Specifications 8.1 Absolute Maximum Ratings 8.2 ESD Ratings 8.3 Recommended Operating Conditions 8.4 Thermal Information: TLV9061 8.5 Thermal Information: TLV9061S 8.6 Thermal Information: TLV9062 8.7 Thermal Information: TLV9062S 8.8 Thermal Information: TLV9064 8.9 Thermal Information: TLV9064S 8.10 Electrical Characteristics 8.11 Typical Characteristics 9 Detailed Description 9.1 Overview 9.2 Functional Block Diagram 9.3 Feature Description 9.3.1 Rail-to-Rail Input 9.3.2 Rail-to-Rail Output 9.3.3 EMI Rejection 9.3.4 Overload Recovery 9.3.5 Shutdown Function 9.4 Device Functional Modes 10 Application and Implementation 10.1 Application Information 10.2 Typical Applications 10.2.1 Typical Low-Side Current Sense Application 10.2.1.1 Design Requirements 10.2.1.2 Detailed Design Procedure 10.2.1.3 Application Curve 11 Power Supply Recommendations 11.1 Input and ESD Protection 12 Layout 12.1 Layout Guidelines 12.2 Layout Example 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation 13.2 Related Links 13.3 Receiving Notification of Documentation Updates 13.4 Community Resources 13.5 Trademarks 13.6 Electrostatic Discharge Caution 13.7 Glossary 14 Mechanical, Packaging, and Orderable Information
SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
www.ti.com Pin Functions: TLV9064 (continued) PIN I/O DESCRIPTION SOIC, NAME WQFN X2QFN TSSOP
NC — 6, 7 — — No internal connection OUT1 1 15 14 O Output, channel 1 OUT2 7 5 6 O Output, channel 2 OUT3 8 8 7 O Output, channel 3 OUT4 14 14 13 O Output, channel 4 V– 11 11 10 I or — Negative (low) supply or ground (for single-supply operation) V+ 4 2 3 I Positive (high) supply 10 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated Product Folder Links: TLV9061 TLV9062 TLV9064 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Description (continued) 6 Device Comparison Table 7 Pin Configuration and Functions 8 Specifications 8.1 Absolute Maximum Ratings 8.2 ESD Ratings 8.3 Recommended Operating Conditions 8.4 Thermal Information: TLV9061 8.5 Thermal Information: TLV9061S 8.6 Thermal Information: TLV9062 8.7 Thermal Information: TLV9062S 8.8 Thermal Information: TLV9064 8.9 Thermal Information: TLV9064S 8.10 Electrical Characteristics 8.11 Typical Characteristics 9 Detailed Description 9.1 Overview 9.2 Functional Block Diagram 9.3 Feature Description 9.3.1 Rail-to-Rail Input 9.3.2 Rail-to-Rail Output 9.3.3 EMI Rejection 9.3.4 Overload Recovery 9.3.5 Shutdown Function 9.4 Device Functional Modes 10 Application and Implementation 10.1 Application Information 10.2 Typical Applications 10.2.1 Typical Low-Side Current Sense Application 10.2.1.1 Design Requirements 10.2.1.2 Detailed Design Procedure 10.2.1.3 Application Curve 11 Power Supply Recommendations 11.1 Input and ESD Protection 12 Layout 12.1 Layout Guidelines 12.2 Layout Example 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation 13.2 Related Links 13.3 Receiving Notification of Documentation Updates 13.4 Community Resources 13.5 Trademarks 13.6 Electrostatic Discharge Caution 13.7 Glossary 14 Mechanical, Packaging, and Orderable Information