IRFP140 www.vishay.com Vishay Siliconix Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L VDS VDS Vary t t p to obtain p required IAS VDD R D.U.T G + V - DD VDS I A AS 10 V t 0.01 p Ω IAS Fig. 12a - Unclamped Inductive Test CircuitFig. 12b - Unclamped Inductive WaveformsFig. 12c - Maximum Avalanche Energy vs. Drain Current S22-0045-Rev. C, 24-Jan-2022 5 Document Number: 91202 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000