Preliminary Datasheet EPC23101 (Efficient Power Conversion) - 7

eGaN® FET DATASHEET
EPC23101
Truth Table VDD VBOOT –VSW HSIN LSIN HS FET LS FET
<UVLO – – – OFF OFF >UVLO <UVLO – 0 OFF OFF >UVLO <UVLO – 1 OFF ON [7] 0 0 OFF OFF 0 1 OFF ON >UVLO 1 0 ON OFF 1 1 OFF [8]
NOTES:
Note 1: Power Stage load current rating is measured using a buck converter application circuit with VIN = 48 V, VOUT = 13.8 V, PWM frequency = 500 kHz, PCB mounted using EPC90142 Evaluation Board, EPC23101 as high side FET and EPC2302 as low side FET, top side heat sink for both devices, 800 LFM airflow, operating at ambient temperature of 25°C with TJ not to exceed 125°C. The rated Power Stage load current specification depends on the application circuit topology, driven low side FET characteristics, duty cycle, power dissipation, maximum allowed junction temperature and thermal management techniques and mechanical stress limit imposed by electromigration. Note 2: Operating PWM switching frequency range is a function of the characteristics of the driven low side FET, power dissipation, maximum allowed junction temperature and minimum duty cycle. The EPC23101 device is capable of operating above 3 MHz PWM switching frequency given appropriate cooling but users need to derate the maximum output current depending on thermal management technique not to exceed TJ = 125°C. Note 3: The minimum input voltage (VIN) should be >= 10 V for the IC to be enabled. Below the minimum VIN the pass-transistor between VDRV and VDD will be off. Same condition when VDD disable pin, EN, is connected to 5 V. Note 4: The output switching node (SW) is clamped above VIN by the HS FET or below GND by the LS FET at their respective source drain voltage in the 3rd quadrant. This is an operating condition when both HS and LS FETs are in the off states during the dead time period which is set by the application circuit with typical value of 15 ns. The Absolute Minimum Rating is determined by LS FET 3rd quadrant clamp voltage below GND. Conversely the Absolute Maximum Rating is determined by HS FET 3rd quadrant clamp voltage above VIN. The time duration that the device can stay in the negative clamp voltage region is subjected to the amount of load current, power dissipation and maximum allowed junction temperature. Note 5: During HS FET or LS FET turn-on transitions with hard switching conditions, the fast di/dt of the HS FET or LS FET coupled with the power loop inductance (VPeak = LPower loop · di/dt) would cause a transient over-voltage spike above VIN or below GND. The Absolute Minimum Rating is amount of peak voltage spike, caused by LS FET di/dt, below GND for less than 2 ns pulse duration. Conversely the Absolute Maximum Rating is amount of peak voltage spike, caused by HS FET di/dt, above VIN, for less than 2 ns pulse duration. Note 6: For interfacing with analog controller operating from 12 VCC and outputting a 12 V drive signal, a resistor network in series should be inserted to divide the voltage to acceptable VIH level and limit the input current into the logic input pins HIN and LIN which is clamped to the VDD supply by ESD protection network. Note 7: LIN commands LS FET to turn-on to charge bootstrap supply through sync boot. Note 8: Internal logic follows HSIN, LSIN respectively but cross conduction lockout logic prevents both HS and LS FETs to turn on together as commanded if both HSIN and LSIN are set to logic “high”. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 7