Preliminary Datasheet EPC23101 (Efficient Power Conversion)

eGaN® FET DATASHEET
EPC23101
EPC23101 – ePower™ Chipset
VIN , 100 V
EFFICIENT POWER CONVERSION
ILoad , 65 A
PRELIMINARY HAL
EPC’s ePowerTM Stage and Chipset integrate input logic interface, level shifting, bootstrap charging and gate drive buffer circuits along with eGaN output FETs. Integration is implemented using EPC’s proprietary GaN IC technology. The end result is a Power Stage that translates logic level input to high voltage and high current power output that is smaller in size, easier to manufacture, simpler to design and more efficient to operate.
Key Parameters PARAMETER VALUE UNIT EPC23101 ePowerTM Chipset
Power Stage Load Current (1 MHz) 65 [1] A Operating PWM Frequency Range 3 [2] MHz
Applications
Absolute Maximum Input Voltage 100 • Buck, Boost, Half-Bridge, Full Bridge or LLC Converters Operating Input Voltage Range 80 V • Single-Phase and Three-Phase Motor Drive Inverter Nominal Bias Supply Voltage 5
Features
Output Current and PWM Frequency Ratings are functions of Operating Conditions. Appropriate derating should be applied to keep T • Integrated high side eGaN® FET with internal gate J at less than 125 °C. See Notes 1 & 2. driver and level shifter
Chipset Information
• Gate driver output to drive external low side eGaN FET
PART NUMBER Rated R
• 5 V external bias supply
DS(on) at 25°C QFN Package Size (mm)
• 3.3 V or 5 V CMOS input logic levels
EPC23101
3.3 mΩ 3.5 x 5 • Independent high side and low side control inputs
EPC2302
1.8 mΩ 3 x 5 • Cross conduction lockout logic keeps both FETs off All exposed pads feature wettable flanks that al ow side wall solder inspection. High voltage and low voltage pads when logic inputs are both high at same time are separated by 0.6 mm spacing to meet IPC rules. Recommended to use EPC2302 as companion low side FET for • External resistors to tune SW switching times and the chipset. over-voltage spikes above rail and below ground
Figure 1: Performance Curves
• Robust level shifter operating for hard and soft switching conditions 98 50 • False trigger immunity from fast switching transients • Synchronous charging for high side bootstrap supply 96 40 • Low quiescent current mode from external VDRV supply when VDD Disable Input pin is pul ed up • Undervoltage lockout for internal low side and high 94 30 side bias supplies • Active gate pul -down for HS FET and LS gate drive with loss of VDRV supply 92 20 • Chipset of compatible
Efficiency (%) Losses (W)
high and low side devices
500 kHz
in QFN packages with 90 10 optimized pinouts
750 kHz
between the two devices
1 MHz
88 0 0 10 20 30 40 50 60 70
I (A) OUT
Buck Converter, VIN = 48 V, VOUT = 12 V, Deadtime = 10 ns, L = 2.2 µH, DCR = 700 µΩ, EPC23101 + EPC2302, Airflow = 1000 LFM. See EPC90142 Quick Start Guide for details (
bit.ly/EPC90142
). EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 1