Preliminary Datasheet EPC23101 (Efficient Power Conversion) - 2

eGaN® FET DATASHEET
EPC23101
Figure 2: Functional Block Diagram
4 CDD V 5 DRV VDD
High side
VBoot 14 C RBoot 13 C DRV V Sync BOOT Enable IN boot VIN 10, 12 logic VIN 3 EN Level Gate shift driver CIN 150 k Logic + SW GND 9, 11 SW UVLO VDRV + 1 HSIN Cross- V R DD DRV 6 over LS LO
EPC2302
2 IN Gate LG Delay OUT 7 match driver GND
EPC23101
8 PGND
General Description
The EPC23101 ePowerTM IC integrates a half-bridge gate driver with an The charging path for the floating bootstrap supply is activated with LSIN internal high side FET. It is designed as part of a chipset with a companion logic. It uses eGaN FET as the series switch that minimizes power losses low side eGaN® FET such as the EPC2302. Integration is implemented by eliminating reverse recovery. This synchronous bootstrap charging using EPC’s proprietary GaN IC technology. The high side monolithic circuit also minimizes voltage drop in the charging path. chip integrates input logic interface, level shifting, bootstrap charging Robust level shifters from low side to high side channels are designed to and gate drive buffer circuits along with a high side eGaN output FET. operate correctly even at large negative clamped voltage and to avoid The low side output FET is driven by the gate driver output of the GaN IC false trigger from fast dv/dt transients including those driven by external to configure a half-bridge power stage. sources or other phases. The on-chip gate drive buffers practical y eliminate effects of common Protection is provided by high side and low side under-voltage lockout source inductance and gate drive loop inductance. Power loop inductance to keep both FETs off at low supply voltages. If the supply voltages drop is minimized by compatible high side to low side pinout configuration even lower or are lost while VIN is active at greater than 10 V, another that facilitates optimal layout technique. Switching times are tuned by active pul -down circuit is used with biasing from VIN to prevent external resistors to achieve 1–3 ns rise and fall times from 0–48 V at ful destructive turn-on of both FETs from gate to drain leakage. load current. Over-voltage spikes can be control ed to less than +10 V The EPC23101 IC is capable of interfacing to digital control ers that use above rail and –10 V below ground during hard switching transitions by standard 3.3 V or 5 V CMOS logic levels. Separate and independent high choosing the tuning resistors, RBOOT and RDRV. side and low side logic control inputs al ow external control ers to set The EPC23101 IC only requires an external 5 V V fixed or adaptive dead times for optimal operating efficiency. Cross DRV power supply. Internal low side and high side power supplies, V conduction prevention logic keeps both FETs off when logic inputs are DD and VBOOT, are generated from the external supply via a series connected switch. The internal both high at the same time. supplies can be cut off to save quiescent power by turning off the switch The FET gate drive voltages are derived from the internal low side and with 5 V applied to the EN pin. high side power supplies. Full gate drive voltages are only available after the HSIN and LSIN PWM inputs start to operate for a few cycles. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 2