Preliminary Datasheet EPC23101 (Efficient Power Conversion) - 3
| Hersteller | Efficient Power Conversion |
| Beschreibung | ePower Chipset 100 V, 65 A |
| Seiten / Seite | 9 / 3 — eGaN® FET DATASHEET. Figure 3: EPC23101 Transparent Top View. Pin Pin … |
| Dateiformat / Größe | PDF / 983 Kb |
| Dokumentensprache | Englisch |
eGaN® FET DATASHEET. Figure 3: EPC23101 Transparent Top View. Pin Pin Name Pin Type Description. 10,
Modelllinie für dieses Datenblatt
Textversion des Dokuments
eGaN® FET DATASHEET
EPC23101
Figure 3: EPC23101 Transparent Top View Pin Pin Name Pin Type Description 12 1
High side PWM logic input, level referenced to GND. Internal pull-down HSIN I resistor is connected between HSIN and GND.
11 2
Low side PWM logic input, level referenced to GND. Internal pull-down resistor LSIN I is connected between LSIN and GND. VDD disable input, level referenced to GND. Internal VDD will be disabled when
10 3
EN I EN is connected to VDRV. VDD will follow VDRV when EN is connected to GND. Internal pull-down resistor is connected between EN and GND.
4
Internal power supply referenced to GND, connect a bypass capacitor from V V DD
9
DD S to GND. External 5 V nominal power supply referenced to GND, connect a bypass
13 5
VDRV S capacitor from VDRV to GND.
8 14 6
Insert resistor between R R DRV to VDRV to control the turn-on slew rate of the DRV O driven low side FET.
7
Low side gate drive output to driven low side FET. Maintain short loop
7
LGOUT O between LGOUT and kelvin source connection of low side FET to minimize
1 2 3 4 5 6
common mode inductance. Logic ground. Connect bypass capacitors between operating bias supplies,
8
GND S, O VDRV and VDD to GND. Low side output gate driver is also referenced to same GND pin.
9,
Output switching node. Connected to output of half-bridge power stage.
11
SW P, S The floating bootstrap power supply, VBOOT , is also referenced to SW. Power bus input. Connected to drain terminal of internal high side FET.
10, 12
VIN P Connect power loop capacitors from VIN to PGND or power source terminals of low side FET.
13
Insert resistor between R R BOOT to VBOOT to control the turn-on slew rate of the BOOT O internal high side FET.
14
Floating bootstrap power supply referenced to SW, connect an external bypass VBOOT S capacitor from VBOOT to SW. Pin Type: P = Power, S = Bias Supplies, I = Logic Inputs, O = Gate Drive Output
Figure 4: EPC2302 Transparent Top View Pin Description 7 1
Gate
2
Source
6 3
Drain
4
Source
5
Drain
5 6
Source
7
Drain
4 3 1 2
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 3
EPC23101
Figure 3: EPC23101 Transparent Top View Pin Pin Name Pin Type Description 12 1
High side PWM logic input, level referenced to GND. Internal pull-down HSIN I resistor is connected between HSIN and GND.
11 2
Low side PWM logic input, level referenced to GND. Internal pull-down resistor LSIN I is connected between LSIN and GND. VDD disable input, level referenced to GND. Internal VDD will be disabled when
10 3
EN I EN is connected to VDRV. VDD will follow VDRV when EN is connected to GND. Internal pull-down resistor is connected between EN and GND.
4
Internal power supply referenced to GND, connect a bypass capacitor from V V DD
9
DD S to GND. External 5 V nominal power supply referenced to GND, connect a bypass
13 5
VDRV S capacitor from VDRV to GND.
8 14 6
Insert resistor between R R DRV to VDRV to control the turn-on slew rate of the DRV O driven low side FET.
7
Low side gate drive output to driven low side FET. Maintain short loop
7
LGOUT O between LGOUT and kelvin source connection of low side FET to minimize
1 2 3 4 5 6
common mode inductance. Logic ground. Connect bypass capacitors between operating bias supplies,
8
GND S, O VDRV and VDD to GND. Low side output gate driver is also referenced to same GND pin.
9,
Output switching node. Connected to output of half-bridge power stage.
11
SW P, S The floating bootstrap power supply, VBOOT , is also referenced to SW. Power bus input. Connected to drain terminal of internal high side FET.
10, 12
VIN P Connect power loop capacitors from VIN to PGND or power source terminals of low side FET.
13
Insert resistor between R R BOOT to VBOOT to control the turn-on slew rate of the BOOT O internal high side FET.
14
Floating bootstrap power supply referenced to SW, connect an external bypass VBOOT S capacitor from VBOOT to SW. Pin Type: P = Power, S = Bias Supplies, I = Logic Inputs, O = Gate Drive Output
Figure 4: EPC2302 Transparent Top View Pin Description 7 1
Gate
2
Source
6 3
Drain
4
Source
5
Drain
5 6
Source
7
Drain
4 3 1 2
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 3