Datasheet ADSP-BF504 (Analog Devices) - 10

ADSP-BF504
• Possibility to synchronize the PWM generation to either • Buffered (8-deep) transmit and receive ports—Each port externally-generated or internally-generated synchroniza- has a data register for transferring data words to and from tion pulses other processor components and shift registers for shifting • Special provisions for BDCM operation (crossover and data in and out of the data registers. output enable functions) • Clocking—Each transmit and receive port can either use an • Wide variety of special switched reluctance (SR) operating external serial clock or generate its own, in frequencies modes ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. • Output polarity and clock gating control • Word length—Each SPORT supports serial data words from 3 to 32 bits in length, transferred most significant bit • Dedicated asynchronous PWM shutdown signal first or least significant bit first. Each PWM block integrates a flexible and programmable • Framing—Each transmit and receive port can run with or 3-phase PWM waveform generator that can be programmed without frame sync signals for each data word. Frame sync to generate the required switching patterns to drive a 3-phase signals can be generated internally or externally, active high voltage source inverter for ac induction motor (ACIM) or or low, and with either of two pulse widths and early or late permanent magnet synchronous motor (PMSM) control. In frame sync. addition, the PWM block contains special functions that considerably simplify the generation of the required PWM • Companding in hardware—Each SPORT can perform switching patterns for control of the electronically commutated A-law or μ-law companding according to ITU recommen- motor (ECM) or brushless dc motor (BDCM). Software can dation G.711. Companding can be selected on the transmit enable a special mode for switched reluctance motors (SRM). and/or receive channel of the SPORT without additional latencies. The six PWM output signals (per PWM unit) consist of three high-side drive signals (PWMx_AH, PWMx_BH, and PWMx- • DMA operation s with single-cycle overhead—Each SPORT _CH) and three low-side drive signals (PWMx_AL, PWMx_BL, can automatically receive and transmit multiple buffers of and PWMx_CL). The polarity of the generated PWM signal can memory data. The processor can link or chain sequences of be set with software, so that either active HI or active LO PWM DMA transfers between a SPORT and memory. patterns can be produced. • Interrupts—Each transmit and receive port generates an The switching frequency of the generated PWM pattern is pro- interrupt upon completing the transfer of a data word or grammable using the 16-bit PWM_TM register. The PWM after transferring an entire data buffer, or buffers, generator can operate in single update mode or double update through DMA. mode. In single update mode, the duty cycle values are pro- • Multichannel capability—Each SPORT supports 128 chan- grammable only once per PWM period, so that the resultant nels out of a 1024-channel window and is compatible with PWM patterns are symmetrical about the midpoint of the PWM the H.100, H.110, MVIP-90, and HMVIP standards. period. In the double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
period. In this mode, it is possible to produce asymmetrical The ADSP-BF504 processors have two SPI-compatible ports PWM patterns that produce lower harmonic distortion in that enable the processor to communicate with multiple SPI- 3-phase PWM inverters. compatible devices. Pulses synchronous to the switching frequency can be generated The SPI interface uses three pins for transferring data: two data internally and output on the PWMx_SYNC pin. The PWM unit pins MOSI (Master Output-Slave Input) and MISO (Master can also accept externally generated synchronization pulses Input-Slave Output) and a clock pin, serial clock (SCK). An SPI through PWMx_SYNC. chip select input pin (SPIx_SS) lets other SPI devices select the Each PWM unit features a dedicated asynchronous shutdown processor, and three SPI chip select output pins (SPIx_SEL3–1) pin, PWMx_TRIP, which (when brought low) instantaneously let the processor select other SPI devices. The SPI select pins are places all six PWM outputs in the OFF state. reconfigured general-purpose I/O pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface,
SERIAL PORTS
which supports both master/slave modes and multimaster The processors incorporate two dual-channel synchronous environments. serial ports (SPORT0 and SPORT1) for serial and multiproces- The SPI port’s baud rate and clock phase/polarities are sor communications. The SPORTs support the following programmable, and it has an integrated DMA channel, features: configurable to support transmit or receive data streams. The • I2S capable operation. DMA channel of the SPI can only service unidirectional accesses at any given time. • Bidirectional operation—Each SPORT has two sets of inde- pendent transmit and receive pins, enabling eight channels of I2S stereo audio. Rev. C | Page 10 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide