Datasheet ADSP-BF504 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | Blackfin Embedded Processor |
| Seiten / Seite | 51 / 2 — ADSP-BF504. TABLE OF CONTENTS. REVISION HISTORY. 06/20—Rev. B to Rev. C |
| Revision | C |
| Dateiformat / Größe | PDF / 1.9 Mb |
| Dokumentensprache | Englisch |
ADSP-BF504. TABLE OF CONTENTS. REVISION HISTORY. 06/20—Rev. B to Rev. C
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ADSP-BF504 TABLE OF CONTENTS
Features ... 1 Dynamic Power Management .. 13 Memory .. 1 ADSP-BF504 Voltage Regulation .. 14 Peripherals ... 1 Clock Signals .. 14 Table of Contents ... 2 Booting Modes ... 16 Revision History .. 2 Instruction Set Description .. 16 General Description ... 3 Development Tools .. 17 Portable Low-Power Architecture ... 3 ACM Interface .. 18 System Integration .. 3 Additional Information .. 19 Processor Peripherals ... 3 Related Signal Chains ... 19 Blackfin Processor Core .. 3 Signal Descriptions ... 20 Memory Architecture .. 5 Specifications .. 22 DMA Controllers .. 9 Operating Conditions ... 22 Watchdog Timer .. 9 Electrical Characteristics ... 24 Timers ... 9 Processor—Absolute Maximum Ratings ... 26 Up/Down Counters and Thumbwheel Interfaces .. 9 ESD Sensitivity ... 26 3-Phase PWM Units .. 9 Processor—Timing Specifications ... 27 Serial Ports .. 10 Processor—Output Drive Currents .. 44 Serial Peripheral Interface (SPI) Ports .. 10 Processor—Test Conditions ... 45 UART Ports (UARTs) .. 11 Processor—Environmental Conditions ... 47 Parallel Peripheral Interface (PPI) ... 11 88-Lead LFCSP Lead Assignment ... 48 RSI Interface .. 12 Outline Dimensions .. 50 Controller Area Network (CAN) Interface .. 12 Ordering Guide ... 51 TWI Controller Interface .. 12 Ports .. 13
REVISION HISTORY 06/20—Rev. B to Rev. C
Changes to ADSP-BF504 Voltage Regulation .. 14 This Rev C product data sheet removes obsolete models and Changes to External Crystal Connections ... 15 associated feature descriptions/specifications, including the Changes to Booting Modes ... 16 integrated 32M bit SPI flash memory, the integrated ADC, and the 120-lead package information. Changes to EZ-KIT Lite Evaluation Kits ... 17 These changes are reflected in the following sections: Changes to Processor—Signal Descriptions .. 20 Changes to Features .. 1 Changes to Operating Conditions .. 22 Changes to Memory ... 1 Changes to Phase-Locked Loop Operating Conditions .. 23 Changes to Peripherals .. 1 Changes to Electrical Characteristics ... 24 Changes to Processor Block Diagram .. 1 Changes to Absolute Maximum Ratings ... 26 Changes to Processor Features .. 3 Changes to Clock and Reset Timing .. 27 Changes to System Integration .. 3 Changes to 88-Lead LFCSP Lead Assignment .. 48 Changes to Memory Architecture .. 5 Changes to Ordering Guide .. 51 Changes to Internal/External Memory Map .. 5 Changes to External (Interface-Accessible) Memory ... 5 Changes to Power Domains .. 14 Rev. C | Page 2 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide
ADSP-BF504 TABLE OF CONTENTS
Features ... 1 Dynamic Power Management .. 13 Memory .. 1 ADSP-BF504 Voltage Regulation .. 14 Peripherals ... 1 Clock Signals .. 14 Table of Contents ... 2 Booting Modes ... 16 Revision History .. 2 Instruction Set Description .. 16 General Description ... 3 Development Tools .. 17 Portable Low-Power Architecture ... 3 ACM Interface .. 18 System Integration .. 3 Additional Information .. 19 Processor Peripherals ... 3 Related Signal Chains ... 19 Blackfin Processor Core .. 3 Signal Descriptions ... 20 Memory Architecture .. 5 Specifications .. 22 DMA Controllers .. 9 Operating Conditions ... 22 Watchdog Timer .. 9 Electrical Characteristics ... 24 Timers ... 9 Processor—Absolute Maximum Ratings ... 26 Up/Down Counters and Thumbwheel Interfaces .. 9 ESD Sensitivity ... 26 3-Phase PWM Units .. 9 Processor—Timing Specifications ... 27 Serial Ports .. 10 Processor—Output Drive Currents .. 44 Serial Peripheral Interface (SPI) Ports .. 10 Processor—Test Conditions ... 45 UART Ports (UARTs) .. 11 Processor—Environmental Conditions ... 47 Parallel Peripheral Interface (PPI) ... 11 88-Lead LFCSP Lead Assignment ... 48 RSI Interface .. 12 Outline Dimensions .. 50 Controller Area Network (CAN) Interface .. 12 Ordering Guide ... 51 TWI Controller Interface .. 12 Ports .. 13
REVISION HISTORY 06/20—Rev. B to Rev. C
Changes to ADSP-BF504 Voltage Regulation .. 14 This Rev C product data sheet removes obsolete models and Changes to External Crystal Connections ... 15 associated feature descriptions/specifications, including the Changes to Booting Modes ... 16 integrated 32M bit SPI flash memory, the integrated ADC, and the 120-lead package information. Changes to EZ-KIT Lite Evaluation Kits ... 17 These changes are reflected in the following sections: Changes to Processor—Signal Descriptions .. 20 Changes to Features .. 1 Changes to Operating Conditions .. 22 Changes to Memory ... 1 Changes to Phase-Locked Loop Operating Conditions .. 23 Changes to Peripherals .. 1 Changes to Electrical Characteristics ... 24 Changes to Processor Block Diagram .. 1 Changes to Absolute Maximum Ratings ... 26 Changes to Processor Features .. 3 Changes to Clock and Reset Timing .. 27 Changes to System Integration .. 3 Changes to 88-Lead LFCSP Lead Assignment .. 48 Changes to Memory Architecture .. 5 Changes to Ordering Guide .. 51 Changes to Internal/External Memory Map .. 5 Changes to External (Interface-Accessible) Memory ... 5 Changes to Power Domains .. 14 Rev. C | Page 2 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide