Datasheet ADSP-BF504 (Analog Devices) - 8

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ADSP-BF504 Table 3. System Interrupt Controller (SIC) (Continued) General-Purpose Peripheral Default Core Peripheral Interrupt Source Interrupt (at Reset) Interrupt ID Interrupt ID SIC Registers
MDMA Stream 1 IVG13 43 6 IAR5 IMASK1, ISR1, IWR1 Software Watchdog Timer IVG13 44 6 IAR5 IMASK1, ISR1, IWR1 Port H Interrupt A IVG13 45 6 IAR5 IMASK1, ISR1, IWR1 Port H Interrupt B IVG13 46 6 IAR5 IMASK1, ISR1, IWR1 ACM Status Interrupt IVG7 47 0 IAR5 IMASK1, ISR1, IWR1 ACM Interrupt IVG10 48 3 IAR6 IMASK1, ISR1, IWR1 Reserved — 49 — IAR6 IMASK1, ISR1, IWR1 Reserved — 50 — IAR6 IMASK1, ISR1, IWR1 PWM0 Trip Interrupt IVG10 51 3 IAR6 IMASK1, ISR1, IWR1 PWM0 Sync Interrupt IVG10 52 3 IAR6 IMASK1, ISR1, IWR1 PWM1 Trip Interrupt IVG10 53 3 IAR6 IMASK1, ISR1, IWR1 PWM1 Sync Interrupt IVG10 54 3 IAR6 IMASK1, ISR1, IWR1 RSI Mask 1 Interrupt IVG10 55 3 IAR6 IMASK1, ISR1, IWR1 Reserved — 56 through 63 — — IMASK1, ISR1, IWR1
Event Control
The processor provides a very flexible mechanism to control the when asserted. A cleared bit in these registers masks the processing of events. In the CEC, three registers are used to corresponding peripheral event, preventing the event from coordinate and control events. Each register is 16 bits wide. propagating to the CEC. • CEC interrupt latch register (ILAT)—Indicates when • SIC interrupt status registers (SIC_ISRx)—As multiple events have been latched. The appropriate bit is set when peripherals can be mapped to a single event, these registers the processor has latched the event and is cleared when the allow the software to determine which peripheral event event has been accepted into the system. This register is source triggered the interrupt. A set bit indicates that the updated automatically by the controller, but it may be writ- peripheral is asserting the interrupt, and a cleared bit indi- ten only when its corresponding IMASK bit is cleared. cates that the peripheral is not asserting the event. • CEC interrupt mask register (IMASK)—Controls the • SIC interrupt wakeup enable registers (SIC_IWRx)—By masking and unmasking of individual events. When a bit is enabling the corresponding bit in these registers, a periph- set in the IMASK register, that event is unmasked and is eral can be configured to wake up the processor should the processed by the CEC when asserted. A cleared bit in the core be idled or in sleep mode when the event is generated. IMASK register masks the event, preventing the processor For more information, see Dynamic Power Management. from servicing the event even though the event may be Because multiple interrupt sources can map to a single general- latched in the ILAT register. This register may be read or purpose interrupt, multiple pulse assertions can occur simulta- written while in supervisor mode. (Note that general- neously, before or during interrupt processing for an interrupt purpose interrupts can be globally enabled and disabled event already detected on this interrupt input. The IPEND reg- with the STI and CLI instructions, respectively.) ister contents are monitored by the SIC as the interrupt • CEC interrupt pending register (IPEND)—The IPEND acknowledgment. register keeps track of all nested events. A set bit in the The appropriate ILAT register bit is set when an interrupt rising IPEND register indicates the event is currently active or edge is detected (detection requires two core clock cycles). The nested at some level. This register is updated automatically bit is cleared when the respective IPEND register bit is set. The by the controller but may be read while in supervisor mode. IPEND bit indicates that the event has entered into the proces- The SIC allows further control of event processing by providing sor pipeline. At this point the CEC recognizes and queues the three pairs of 32-bit interrupt control and status registers. Each next rising edge event on the corresponding event input. The register contains a bit, corresponding to each of the peripheral minimum latency from the rising edge transition of the general- interrupt events shown in Table 3. purpose interrupt to the IPEND output asserted is three core • SIC interrupt mask registers (SIC_IMASKx)—Control the clock cycles; however, the latency can be much higher, depend- masking and unmasking of each peripheral interrupt event. ing on the activity within and the state of the processor. When a bit is set in these registers, the corresponding peripheral event is unmasked and is forwarded to the CEC Rev. C | Page 8 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide