Datasheet ADSP-21065L (Analog Devices) - 5

ADSP-21065L
I/O transfers). Programs can be downloaded to the ADSP-21065L
DEVELOPMENT TOOLS
using DMA transfers. Asynchronous off-chip peripherals can The ADSP-21065L is supported with a complete set of software control two DMA channels using DMA Request/Grant lines and hardware development tools, including the EZ-ICE® In- (DMAR DMAG 1-2, 1-2). Other DMA features include interrupt Circuit Emulator and development software. generation on completion of DMA transfers and DMA chaining The same EZ-ICE hardware that you use for the ADSP-21060/ for automatically linked DMA transfers. ADSP-21062 also fully emulates the ADSP-21065L.
Serial Ports
Both the SHARC Development Tools family and the VisualDSP® The ADSP-21065L features two synchronous serial ports that integrated project management and debugging environment provide an inexpensive interface to a wide variety of digital and support the ADSP-21065L. The VisualDSP project management mixed-signal peripheral devices. The serial ports can operate at environment enables you to develop and debug an application 1x clock frequency, providing each with a maximum data rate of from within a single integrated program. 33 Mbit/s. Each serial port has a primary and a secondary set of transmit and receive channels. Independent transmit and receive The SHARC Development Tools include an easy to use Assem- functions provide greater flexibility for serial communications. bler that is based on an algebraic syntax; an Assembly library/ Serial port data can be automatically transferred to and from librarian; a linker; a loader; a cycle-accurate, instruction-level on-chip memory via DMA. Each of the serial ports supports simulator; a C compiler; and a C run-time library that includes three operation modes: DSP serial port mode, I2S mode (an DSP and mathematical functions. interface commonly used by audio codecs), and TDM (Time Debugging both C and Assembly programs with the Visual DSP Division Multiplex) multichannel mode. debugger, you can: The serial ports can operate with little-endian or big-endian • View Mixed C and Assembly Code transmission formats, with selectable word lengths of 3 bits to • Insert Break Points 32 bits. They offer selectable synchronization and transmit • Set Watch Points modes and optional m-law or A-law companding. Serial port • Trace Bus Activity clocks and frame syncs can be internally or externally generated. • Profile Program Execution The serial ports also include keyword and keymask features to • Fill and Dump Memory enhance interprocessor communication. • Create Custom Debugger Windows
Programmable Timers and General-Purpose I/O Ports
The Visual IDE enables you to define and manage multiuser The ADSP-21065L has two independent timer blocks, each of projects. Its dialog boxes and property pages enable you to which performs two functions—Pulsewidth Generation and configure and manage all of the SHARC Development Tools. Pulse Count and Capture. This capability enables you to: In Pulsewidth Generation mode, the ADSP-21065L can gener- • Control how the development tools process inputs and gen- ate a modulated waveform with an arbitrary pulsewidth within erate outputs. a maximum period of 71.5 secs. • Maintain a one-to-one correspondence with the tool’s com- In Pulse Counter mode, the ADSP-21065L can measure either mand line switches. the high or low pulsewidth and the period of an input waveform. The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access The ADSP-21065L also contains twelve programmable, general port of the ADSP-21065L processor to monitor and control the purpose I/O pins that can function as either input or output. As target board processor during emulation. The EZ-ICE provides output, these pins can signal peripheral devices; as input, these full-speed emulation, allowing inspection and modification of pins can provide the test for conditional branching. memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG inter-
Program Booting
face—the emulator does not affect target system loading or timing. The internal memory of the ADSP-21065L can be booted at system power-up from an 8-bit EPROM, a host processor, or In addition to the software and hardware development tools external memory. Selection of the boot source is controlled by available from Analog Devices, third parties provide a wide the BMS (Boot Memory Select) and BSEL (EPROM Boot) range of tools supporting the SHARC processor family. Hard- pins. Either 8-, 16-, or 32-bit host processors can be used for ware tools include SHARC PC plug-in cards multiprocessor booting. For details, see the descriptions of the BMS and BSEL SHARC VME boards, and daughter and modules with multiple pins in the Pin Descriptions section of this data sheet. SHARCs and additional memory. These modules are based on the SHARCPAC™ module specification. Third Party software
Multiprocessing
tools include an Ada compiler, DSP libraries, operating systems, The ADSP-21065L offers powerful features tailored to multi- and block diagram design tools. processing DSP systems. The unified address space allows direct interprocessor accesses of both ADSP-21065L’s IOP
Additional Information
registers. Distributed bus arbitration logic is included on-chip For detailed information on the ADSP-21065L instruction set for simple, glueless connection of systems containing a maximum and architecture, see the ADSP-21065L SHARC User’s Manual, of two ADSP-21065Ls and a host processor. Master processor Third Edition, and the ADSP-21065L SHARC Technical Reference. changeover incurs only one cycle of overhead. Bus lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is EZ-ICE and VisualDSP are registered trademarks of Analog Devices, Inc. 132 Mbytes/sec over the external port. SHARCPAC is a trademark of Analog Devices, Inc. REV. C –5– Document Outline SUMMARY KEY FEATURES Flexible Data Formats and 40-Bit Extended Precision Parallel Computations 544 Kbits Configurable On-Chip SRAM DMA Controller Host Processor Interface Multiprocessing Serial Ports GENERAL DESCRIPTION ADSP-21000 FAMILY CORE ARCHITECTURE Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Two Operands Instruction Cache Data Address Generators with Hardware Circular Buffers Flexible Instruction Set ADSP-21065L FEATURES Dual-Ported On-Chip Memory Off-Chip Memory and Peripherals Interface SDRAM Interface Host Processor Interface DMA Controller Serial Ports Programmable Timers and General-Purpose I/O Ports Program Booting Multiprocessing DEVELOPMENT TOOLS Additional Information PIN DESCRIPTIONS CLOCK SIGNALS TARGET BOARD CONNECTOR FOR EZ-ICE PROBE SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION ADSP-21065L TIMING SPECIFICATIONS General Notes Memory Read—Bus Master Memory Write—Bus Master Synchronous Read/Write—Bus Master Synchronous Read/Write—Bus Slave Multiprocessor Bus Request and Host Bus Request Asynchronous Read/Write—Host to ADSP-21065L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS DMA Handshake SDRAM Interface—Bus Master SDRAM Interface—Bus Slave Serial Ports JTAG Test Access Port and Emulation OUTPUT DRIVE CURRENT TEST CONDITIONS Output Disable Time Example System Hold Time Calculation Capacitive Loading POWER DISSIPATION ENVIRONMENTAL CONDITIONS Thermal Characteristics 208-LEAD MQFP PIN CONFIGURATION 208-LEAD MQFP PIN OUTLINE DIMENSIONS 208-Lead Plastic Quad Flatpack Package [MQFP] 196-BALL MINI-BGA PIN CONFIGURATION 196-BALL MINI-BGA PIN CONFIGURATION ORDERING GUIDE OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] Revision History