Datasheet ADSP-21065L (Analog Devices)

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DSP Microcomputer ADSP-21065L SUMMARY SDRAM Controller for Glueless Interface to Low Cost High Performance Signal Computer for Communica- External Memory (@ 66 MHz) tions, Audio, Automotive, Instrumentation and 64M Words External Address Range Industrial Applications 12 Programmable I/O Pins and Two Timers with Event Super Harvard Architecture Computer (SHARC®) Capture Options Four Independent Buses for Dual Data, Instruction, Code-Compatible with ADSP-2106x Family and I/O Fetch on a Single Cycle 208-Lead MQFP or 196-Ball Mini-BGA Package 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating- 3.3 Volt Operation Point Arithmetic Flexible Data Formats and 40-Bit Extended Precision 544 Kbits On-Chip SRAM Memory and Integrated I/O 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Peripheral Floating-Point Data Formats I2S Support, for Eight Simultaneous Receive and Trans- 32-Bit Fixed-Point Data Format, Integer and Fractional, mit Channels with Dual 80-Bit Accumulators KEY FEATURES Parallel Computations 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Single-Cycle Multiply and ALU Operations in Parallel with Performance Dual Memory Read/Writes and Instruction Fetch User-Configurable 544 Kbits On-Chip SRAM Memory Multiply with Add and Subtract for Accelerated FFT But- Two External Port, DMA Channels and Eight Serial terfly Computation Port, DMA Channels 1024-Point Complex FFT Benchmark: 0.274 ms (18,221 Cycles) CORE PROCESSOR DUAL-PORTED SRAM JTAG 7 INSTRUCTION TWO INDEPENDENT CACHE DUAL-PORTED BLOCKS TEST & 32
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48 BIT EMULATION PROCESSOR PORT I/O PORT BLOCK 0 BLOCK 1 ADDR DATA DATA ADDR ADDR DATA ADDR DATA EXTERNAL DAG1 DAG2 PROGRAM PORT 8
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32 8
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24 SEQUENCER SDRAM IOA IOD INTERFACE 24 PM ADDRESS BUS 17 48 24 ADDR BUS 32 DM ADDRESS BUS MUX MULTIPROCESSOR INTERFACE 48 PM DATA BUS 32 BUS DATA BUS CONNECT 40 DM DATA BUS MUX (PX) HOST PORT 4 DATA DMA IOP REGISTER CONTROLLER REGISTERS FILE (MEMORY MAPPED) (2 Rx, 2Tx) 16
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40 BIT BARREL MULTIPLIER ALU SPORT 0 CONTROL, SHIFTER (I2S) STATUS, TIMER & (2 Rx, 2Tx) DATA BUFFERS SPORT 1 (I2S) I/O PROCESSOR
Figure 1. Functional Block Diagram SHARC is a registered trademark of Analog Devices, Inc. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise
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Document Outline SUMMARY KEY FEATURES Flexible Data Formats and 40-Bit Extended Precision Parallel Computations 544 Kbits Configurable On-Chip SRAM DMA Controller Host Processor Interface Multiprocessing Serial Ports GENERAL DESCRIPTION ADSP-21000 FAMILY CORE ARCHITECTURE Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Two Operands Instruction Cache Data Address Generators with Hardware Circular Buffers Flexible Instruction Set ADSP-21065L FEATURES Dual-Ported On-Chip Memory Off-Chip Memory and Peripherals Interface SDRAM Interface Host Processor Interface DMA Controller Serial Ports Programmable Timers and General-Purpose I/O Ports Program Booting Multiprocessing DEVELOPMENT TOOLS Additional Information PIN DESCRIPTIONS CLOCK SIGNALS TARGET BOARD CONNECTOR FOR EZ-ICE PROBE SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION ADSP-21065L TIMING SPECIFICATIONS General Notes Memory Read—Bus Master Memory Write—Bus Master Synchronous Read/Write—Bus Master Synchronous Read/Write—Bus Slave Multiprocessor Bus Request and Host Bus Request Asynchronous Read/Write—Host to ADSP-21065L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS DMA Handshake SDRAM Interface—Bus Master SDRAM Interface—Bus Slave Serial Ports JTAG Test Access Port and Emulation OUTPUT DRIVE CURRENT TEST CONDITIONS Output Disable Time Example System Hold Time Calculation Capacitive Loading POWER DISSIPATION ENVIRONMENTAL CONDITIONS Thermal Characteristics 208-LEAD MQFP PIN CONFIGURATION 208-LEAD MQFP PIN OUTLINE DIMENSIONS 208-Lead Plastic Quad Flatpack Package [MQFP] 196-BALL MINI-BGA PIN CONFIGURATION 196-BALL MINI-BGA PIN CONFIGURATION ORDERING GUIDE OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] Revision History