link to page 15 link to page 25 link to page 15 link to page 15 link to page 15 link to page 15 link to page 15 link to page 15 link to page 15 link to page 15 link to page 15 link to page 15 ADuCM355Data SheetParameter SymbolMinTypMaxUnitTestConditions/Comments PGA Mismatch Error1 PGA Gain Mismatch Drift 1.5 μV/°C Drift after calibration Uncalibrated PGA Gain Mismatch 4 % Production devices only calibrated for PGA gain = 1.5 Uncalibrated PGA Gain Mismatch 10 μV/°C Uncalibrated drift Drift ADC DYNAMIC PERFORMANCE Input signal frequency (fIN) = 20 kHz sine wave, fSAMPLE = 200 kSPS, using AINx voltage input channels, PGA gain = 1.5 Signal-to-Noise Ratio SNR Includes distortion and noise components 80 dB PGA gain = 1, 1.5, and 2 76 dB PGA gain = 4 70 dB PGA gain = 9 Total Harmonic Distortion1 THD −84 dB Peak Harmonic or Spurious Noise1 −86 dB Channel to Channel Crosstalk1 −86 dB Measured on adjacent channels Noise (RMS)1, 5 See 0.1 Hz to 10 Hz Table 2 800 nV/√Hz Chop off 400 nV/√Hz Chop on ADC INPUT Input to ADC mux Input Voltage Ranges1 0.2 2.1 V Voltage applied to any input pin Pseudo Differential Voltage Between ADCVBIAS_CAP pin voltage (1.82 V) and analog input from mux −0.9 +0.9 V Gain = 1 −0.9 +0.9 V Gain = 1.5 −0.6 +0.6 V Gain = 2 −0.3 +0.3 V Gain = 4 −0.133 +0.133 V Gain = 9 Input Range1 ±0.00005 ±3000 μA Low power TIA 0, low power TIA 1, and HPTIA current input channel ranges Common-Mode Range1 0.2 1.1 2.1 V Leakage Current −1.5 ±0.5 +1.5 nA AIN0 to AIN7_LPF1, SE0, and SE1 pins (exclusive of DE0 and DE1 pins) ±2 nA DE0 and DE1 pins only, see Figure 14 Input Current1 −8 ±2 +8 nA AIN0 to AIN7_LPF1, SE0, SE1, and DE0 pins Input Capacitance 40 pF During ADC acquisition AAF, 3 dB Frequency Range 3 programmable settings Mode 0 50 kHz Mode 1 100 kHz Mode 2 250 kHz ADC Channel Switch Settling Time Time delay required after switching ADC input channel, excludes sinc3 settling time AAF, 3 dB Cutoff Frequency1 250 kHz 25 μs 100 kHz 40 μs 50 kHz 60 μs Rev. C | Page 6 of 28 Document Outline FEATURES APPLICATIONS SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS RMS NOISE RESOLUTION OF ADC TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION RECOMMENDED CIRCUIT AND COMPONENT VALUES OUTLINE DIMENSIONS ORDERING GUIDE