Datasheet ADUCM355 (Analog Devices) - 5

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Data Sheet ADuCM355 SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS
AVDD = DVDD = 2.8 V to 3.6 V, maximum difference between supplies = 0.3 V, ADC reference and excitation DAC and amplifier = 1.82 V internal reference, low power VBIASx and VZEROx DAC reference = 2.5 V internal reference, central processing unit (CPU) speed (fCORE) = 26 MHz, TA = −40°C to +85°C, buck convertor on digital die disabled, unless otherwise noted.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
ADC SPECIFICATIONS Pseudo differential mode measured relative to ADCVBIAS_CAP pin voltage (1.82 V) unless otherwise stated, specifications based on high speed mode unless otherwise stated, ADC voltage channel calibrated in production with PGA gain = 1.5, AFE die analog clock (ACLK) = 32 MHz or 16 MHz unless otherwise stated Data Rate1 fSAMPLE 400 kSPS High speed mode, decimation factor of 4 fSAMPLE 200 kSPS Normal mode, decimation factor of 4 Resolution1 16 Bits Number of data bits Integral Nonlinearity1 INL −4 ±2.0 +4.0 LSB PGA Gain = 1.5, 1.82 V internal reference, 1 LSB2 = (1.82 V/215)/PGA gain −5.6 ±2.0 +4.7 LSB PGA gain = 9, 1.82 V internal reference ±2.0 LSB 1.82 V external reference, 1 LSB2 = (1.82 V/215)/PGA gain Differential Nonlinearity (No Missing DNL −0.99 ±0.9 +2.5 LSB 1.82 V internal reference, 1 LSB2 = Codes)1 (1.82 V/215)/PGA gain DC Code Distribution3 ±6 LSB Minimum and maximum range from mean ADC codes for 1000 ADC samples, PGA gain = 1.5, low power mode, ADC input 0.9 V, ADC output data rate = 200 kSPS, 1 LSB2 = (1.82 V/215)/PGA gain ±6 LSB Input channel is low power TIA 0 = 1 μA, TIA resistor (RTIA) = 512 kΩ, load resistor (RLOAD) = 10 Ω, ADC output data rate = 200 kSPS ±6 LSB Input channel is high power TIA (HPTIA) = 1 μA, RTIA = 10 kΩ, RLOAD = 100 Ω, ADC output data rate = 200 kSPS ADC ENDPOINT ERRORS For AIN0 to AIN7_LPF1 inputs, 200 kSPS ADC update rate, sinc3 filter enabled Offset Error −600 ±200 +600 μV PGA gain = 1.5, low power mode, all channels except AIN3 −620 ±200 +880 μV PGA gain = 1.5, low power mode, AIN3 only High Power Mode4 −1.1 ±0.5 +1.4 mV PGA gain = 1.5, high power mode Drift1 ±3 μV/°C Using 1.82 V internal reference Offset Matching ±2 LSB Matching compared to AIN3 Full-Scale Error −750 ±400 +940 μV Excluding internal channels, both negative and positive full scale, error at both endpoints, PGA gain = 1.5, low power mode High Power Mode4 −1.6 ±0.8 +1.82 mV PGA gain = 1.5, high power mode Internal Channels1 0.2 0.75 % of full AVDD/2, DVDD/2, ADCVBIAS_CAP, scale VREF_2.5V, VREF_1.8V, AVDD_REG Gain Drift1 −3 ±1 +3 μV/°C Full-scale error drift minus offset error drift Gain Error Matching ±3 LSB Mismatch from channel to channel Rev. C | Page 5 of 28 Document Outline FEATURES APPLICATIONS SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS RMS NOISE RESOLUTION OF ADC TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION RECOMMENDED CIRCUIT AND COMPONENT VALUES OUTLINE DIMENSIONS ORDERING GUIDE