Datasheet ADUCM355 (Analog Devices) - 10

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ADuCM355 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
BUFFERED REFERENCE VOLTAGE 1.82 V OUTPUT Accuracy ±5 mV TA = 25°C, capacitive load to ground 100 pF Reference Temperature Coefficient1, 5 −20 +20 ppm/°C Output Impedance 0.5 1 Ω Load Current1 200 μA LOW POWER DAC SPECIFICATIONS VBIASx specifications derived from (VBIASx/VZEROx) measurements taken with potentiostat amplifier in unity-gain mode and measured at CE0 and CE1 pins, VZEROx specifications derived from measurements at VZERO0 and VZERO1 pins, dual output low power DACs Resolution1 12 Bits 12-bit mode 6 Bits 6-bit mode Relative Accuracy1, 10, 11 INL −6.5 ±1 +3 LSB 12-bit mode, 1 LSB = 2.2 V/(212 − 1) −2.5 ±0.1 +2 LSB 6-bit mode, 1 LSB = 2.2 V/26 Differential Nonlinearity9 DNL −0.99 +2.5 LSB 12-bit mode, guaranteed monotonic, 1 LSB = 2.2 V/(212 − 1) −0.5 +0.5 LSB 6-bit mode, guaranteed monotonic, 1 LSB = 2.2 V/26 Offset Error1 ±1 ±7 mV VBIASx/VZEROx in 12-bit mode, 2.5 V internal reference, DAC output code 0x000, target 0x000 code is 200 mV −1 ±0.2 +1 mV Differential offset voltage of VBIASx referred to VZEROx, LPDACDATx = 0x00000 Drift ±5 μV/°C VBIASx or VZER0x referred to AGND, using internal low power reference Differential Offset VBIASx to 4 μV/°C Differential offset voltage of VBIASx VZEROx ≈ 0 V1 referred to VZEROx, TA = −40°C to +60°C, LPDACDATx = 0x1A680 Differential offset VBIASx to 10 μV/°C Differential offset voltage of VBIAS referred VZEROx ≈ ±600 mV1 to VZEROx, TA = −40°C to +60°C, LPDACDATx = 0x1AAE0 Gain Error1 ±0.2 ±0.5 % 12-bit mode, DAC code = 0xFFF with target voltage of 2.4 V, no correction for internal 2.5 V reference drift Drift 10 ppm/°C Using internal low power reference Mismatch ±0.1 % % of full scale on VBIAS0 to VBIAS1 in 12-bit mode Analog Outputs Output Voltage Range1 LSB size is 2.2/(212 − 1), input common- mode voltage of low power potentiostat and low power TIA is AVDD − 600 mV 12-Bit Outputs 0.2 2.4 V AVDD ≥ 2.8 V 0.2 2.3 V AVDD < 2.8 V, LPDACDATx, Bits[11:0] = 0xF40 LSB size is 2.2/26, input common-mode voltage of low power potentiostat and low power TIA is AVDD − 600 mV 6-Bit Outputs 0.2 2.366 V AVDD ≥ 2.8 V 0.2 2.3 V AVDD < 2.8 V, LPDACDATx, Bits[17:12] = 0x3D AVDD to VBIASx and VZEROx 400 mV Minimum headroom between AVDD, Headroom Voltage1 VBIASx, and VZEROx output voltage, increases to 600 mV if connected to low power TIA or low power potentiostat amplifiers Output Impedance1 1.65 MΩ Rev. C | Page 10 of 28 Document Outline FEATURES APPLICATIONS SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS RMS NOISE RESOLUTION OF ADC TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION RECOMMENDED CIRCUIT AND COMPONENT VALUES OUTLINE DIMENSIONS ORDERING GUIDE