Datasheet 5P35021 (IDT) - 3

5P35021 Datasheet
Block Diagram
DIV1/REF VDDDIFF2 OSC DIFF2 MUX MU DIV1 DIV3 MUX MU DIFF2B CLKINB/X1 PLL1 VDDDIFF1 DIV1/REF CLKIN/X2 DIV2 DIFF1 DIV3 MUX MU DIFF1B Power VBAT MUX MU DIV3 MUX MU PLL2 Monitor VDD33 MUX MU DIV4 POR VDDA MUX MU PLL3 DIV5 DIV4/REF Calibration OE1 VSS DIV5 MUX MU SE1 32K VDDSE1 32.768K DCO SCL_DFC1 Overshoot Reduction I2C Engine Dynamic Frequency Control Logic (DFC) (ORT) SDA_DFC0 OTP memory (1 configuration) Proactive Power Saving Logic (PPS) Timer
Pin Assignments Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View
FF2 IFF2 IFF1 SD FF2 FF2B VS DI DI VDDDI VSSD 20 19 18 17 16 VDDA 1 15 DIFF1 SDA_DFCO 2 14 DIFF1B SEL_DFC/SCL_DFC1 3
5P35021
13 VDDDIFF1 4 12 CLKIN/X2 OE1 5 CLKINB/X1 11 SE1 6 7 8 9 10 S 3 VBAT VS SE1 VDD3 D VSSSE1 VD ©2019 Integrated Device Technology, Inc. 3 October 4, 2019 Document Outline Description Typical Applications Key Specifications Features Output Features Block Diagram Pin Assignments Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Sources Table 3. Output Source Table 4. Output Source Selection Register Settings Table 5. DIFF1 Output Table 6. DIFF2 Output Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Timer Function Description Figure 5. Timer Functions OE Pin Function Table 8. OE Pin Functions Table 9. OE Pin Function Summary Table 10. PD# Priority Reference Input and Selection Crystal Input (X1/X2) Table 11. Programmable Tuning Caps Spread Spectrum Analog Spread Spectrum Digital Spread Spectrum Figure 6. Digital Spread Spectrum VBAT Table 12. VBAT Switching Threshold ORT–VCO Overshoot Reduction Technology PLL Features and Descriptions Table 13. Output 1 Divider Table 14. Output 2, 4, and 5 Divider Table 15. Output 3 Divider Output Clock Test Conditions Figure 7. LVCMOS Output Test Conditions Figure 8. LP-HCSL Output Test Conditions Absolute Maximum Ratings Table 16. Absolute Maximum Ratings Recommended Operating Conditions Table 17. Recommended Operating Conditions Electrical Characteristics Table 18. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Table 19. Crystal Characteristics Table 20. DC Electrical Characteristics (Industrial)1,2 Table 21. DC Electrical Characteristics (Automotive)1,2 Table 22. Input Parameters1,2 Table 23. Power Consumption of 32.768kHz Output Only Operation Table 24. DC Electrical Characteristics – 3.3V LVCMOS Table 25. DC Electrical Characteristics – 2.5V LVCMOS Table 26. DC Electrical Characteristics – 1.8V LVCMOS Table 27. Electrical Characteristics – DIF 0.7V LPHCSL Differential Outputs Table 28. Electrical Characteristics – LVDS Table 29. Electrical Characteristics – LVPECL Figure 9. Output Differential Voltage Swing AC Electrical Characteristics Table 30. AC Electrical Characteristics PCI Express Jitter Specifications Table 31. PCI Express Jitter Specifications Spread Spectrum Generation Specifications Table 32. Spread Spectrum Generation Specifications I2C Bus Characteristics Table 33. I2C Bus DC Characteristics Table 34. I2C Bus AC Characteristics I2C Mode Operations Figure 10. I2C Slave Read and Write Cycle Sequencing Glossary of Features Table 35. Glossary of Features Package Outline Drawings Marking Diagrams (industrial) Marking Diagrams (automotive) Ordering Information Revision History