Datasheet 5P35021 (IDT) - 5

5P35021 Datasheet
Power Group Table 2. Power Group Power Supply SE DIFF DIV MUX PLL DCO REF Xtal
VDDSE1 SE1 1 VDDDIFF1 DIFF1 DIV3/4 MUXPLL2 PLL2 VDDDIFF2 DIFF2 DIV1 MUXPLL1 VDD33 DIV5 PLL3 DCO REF Xtal V 1 BAT DCO Xtal VDDA DIV2 PLL1 1 VDDSE1 for non-32kHz outputs should be OFF when VDDA/VDD33 turns OFF; VBAT mode only supports 32.768kHz outputs from SE1.
Output Sources Table 3. Output Source Outputs Source REF SE1 DIFF1 DIFF2
Xtal REF Xtal REF Xtal REF 32.768kHz 32.768kHz PLL1 PLL1 PLL1 PLL2 PLL2 PLL2 PLL2 PLL3 PLL3 PLL3 PLL3
Table 4. Output Source Selection Register Settings SE1 B36<4> B36<3> B31<1> B29<3>
From 32kHz 0 1 0 0 From PLL3 + Divider 5 1 0 0 0 From PLL2 + Divider 4 1 1 1 0 From REF + Divider 4 1 1 0 1
Table 5. DIFF1 Output DIFF1 B34<7> B0<3>
From PLL1 + Divider 1 0 0 From PLL2/3 + Divider 3 1 0 From REF + Divider 1 0 1 ©2019 Integrated Device Technology, Inc. 5 October 4, 2019 Document Outline Description Typical Applications Key Specifications Features Output Features Block Diagram Pin Assignments Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Sources Table 3. Output Source Table 4. Output Source Selection Register Settings Table 5. DIFF1 Output Table 6. DIFF2 Output Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Timer Function Description Figure 5. Timer Functions OE Pin Function Table 8. OE Pin Functions Table 9. OE Pin Function Summary Table 10. PD# Priority Reference Input and Selection Crystal Input (X1/X2) Table 11. Programmable Tuning Caps Spread Spectrum Analog Spread Spectrum Digital Spread Spectrum Figure 6. Digital Spread Spectrum VBAT Table 12. VBAT Switching Threshold ORT–VCO Overshoot Reduction Technology PLL Features and Descriptions Table 13. Output 1 Divider Table 14. Output 2, 4, and 5 Divider Table 15. Output 3 Divider Output Clock Test Conditions Figure 7. LVCMOS Output Test Conditions Figure 8. LP-HCSL Output Test Conditions Absolute Maximum Ratings Table 16. Absolute Maximum Ratings Recommended Operating Conditions Table 17. Recommended Operating Conditions Electrical Characteristics Table 18. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Table 19. Crystal Characteristics Table 20. DC Electrical Characteristics (Industrial)1,2 Table 21. DC Electrical Characteristics (Automotive)1,2 Table 22. Input Parameters1,2 Table 23. Power Consumption of 32.768kHz Output Only Operation Table 24. DC Electrical Characteristics – 3.3V LVCMOS Table 25. DC Electrical Characteristics – 2.5V LVCMOS Table 26. DC Electrical Characteristics – 1.8V LVCMOS Table 27. Electrical Characteristics – DIF 0.7V LPHCSL Differential Outputs Table 28. Electrical Characteristics – LVDS Table 29. Electrical Characteristics – LVPECL Figure 9. Output Differential Voltage Swing AC Electrical Characteristics Table 30. AC Electrical Characteristics PCI Express Jitter Specifications Table 31. PCI Express Jitter Specifications Spread Spectrum Generation Specifications Table 32. Spread Spectrum Generation Specifications I2C Bus Characteristics Table 33. I2C Bus DC Characteristics Table 34. I2C Bus AC Characteristics I2C Mode Operations Figure 10. I2C Slave Read and Write Cycle Sequencing Glossary of Features Table 35. Glossary of Features Package Outline Drawings Marking Diagrams (industrial) Marking Diagrams (automotive) Ordering Information Revision History