Datasheet AD73311L (Analog Devices) - 8

AD73311L TERMINOLOGY ABBREVIATIONS Absolute Gain
ADC Analog-to-Digital Converter. Absolute gain is a measure of converter gain for a known signal. ALB Analog Loop-Back. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at 0 dBm0 BW Bandwidth. for the ADC. The absolute gain specification is used for gain CRx A Control Register where x is a placeholder for an tracking error specification. alphabetic character (A–E). There are five read/
Crosstalk
write control registers on the AD73311L—desig- Crosstalk is due to coupling of signals from a given channel nated CRA through CRE. to an adjacent channel. It is defined as the ratio of the ampli- CRx:n A bit position, where n is a placeholder for a tude of the coupled signal to the amplitude of the input signal. numeric character (0–7), within a control register; Crosstalk is expressed in dB. where x is a placeholder for an alphabetic charac-
Gain Tracking Error
ter (A–E). Position 7 represents the MSB and Gain tracking error measures changes in converter output for Position 0 represents the LSB. different signal levels relative to an absolute signal level. The DAC Digital-to-Analog Converter. absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz DLB Digital Loop-Back. for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0 DMCLK Device (Internal) Master Clock. This is the (DAC) is 0 dB by definition. internal master clock resulting from the external master clock (MCLK) being divided by the on-chip
Group Delay
master clock divider. Group delay is defined as the derivative of radian phase with respect to radian frequency, dø(f)/df. Group delay is a measure FSLB Frame Sync Loop-Back—where the SDOFS of of average delay of a system as a function of frequency. A linear the final device in a cascade is connected to the system with a constant group delay has a linear phase response. RFS and TFS of the DSP and the SDIFS of first The deviation of group delay from a constant indicates the degree device in the cascade. Data input and output of nonlinear phase response of the system. occur simultaneously. In the case of nonFSLB, SDOFS and SDO are connected to the Rx Port
Idle Channel Noise
of the DSP while SDIFS and SDI are connected Idle channel noise is defined as the total signal energy measured to the Tx Port. at the output of the device when the input is grounded (measured in the frequency range 300 Hz–3400 Hz). PGA Programmable Gain Amplifier.
Intermodulation Distortion
SC Switched Capacitor. With inputs consisting of sine waves at two frequencies, fa and SNR Signal-to-Noise Ratio. fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where SPORT Serial Port. m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which THD Total Harmonic Distortion. neither m nor n are equal to zero. For final testing, the second VBW Voice Bandwidth. order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to noise on the power supply. Power supply rejection is measured by modulating the power supply with a sine wave and measuring the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which the ADC updates its out- put register and the DAC updates its output from its input register. It is fixed relative to the DMCLK (= DMCLK/256) and therefore may only be changed by changing the DMCLK.
SNR+THD
Signal-to-noise ratio plus harmonic distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components in the frequency range 300 Hz–3400 Hz, including harmonics but excluding dc. –8– REV. A