Datasheet AD9284 (Analog Devices) - 8

AD9284 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS B A DD DD DD EF DD DD DD IN–B IN+ CM IN+ IN–A AV V V AV AV VR AV V AV V V AV 48 47 46 45 44 43 42 41 40 39 38 37 AVDD 1 36 AVDD PIN 1 AVDD 2 35 AVDD INDICATOR DNC 3 34 CLK+ DNC 4 33 CLK– RBIAS 5 32 CSB AD9284 DNC 6 31 SDIO/PWDN DRGND 7 TOP VIEW 30 SCLK (Not to Scale) DRVDD 8 29 OE D0– (LSB) 9 28 DRGND D0+ (LSB) 10 27 DRVDD D1– 11 26 D7+ (MSB) D1+ 12 25 D7– (MSB) 13 14 15 16 17 18 19 20 21 22 23 24 – + D2– D2+ D3– D3+ D4– D4+ D5– D5+ D6– D6+ DCO DCO NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG
003
GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
09085- Figure 3. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description
ADC Power Pins 1, 2, 35, 36, 37, 40, 42, AVDD Supply Analog Power Supply (1.8 V Nominal). 44, 45, 48 8, 27 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 7, 28 DRGND Ground Digital Output Ground. 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. This is the only ground connection, and it must be soldered to the PCB analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. ADC Analog Pins 39 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 46 VIN+B Input Differential Analog Input Pin (+) for Channel B. 47 VIN−B Input Differential Analog Input Pin (−) for Channel B. 43 VREF Input/output Voltage Reference Input/Output. 5 RBIAS Input/output External Reference Bias Resistor. Connect 10 kΩ from RBIAS to AGND. 41 VCM Output Common-Mode Level Bias Output for Analog Inputs. 34 CLK+ Input ADC Clock Input—True. 33 CLK− Input ADC Clock Input—Complement. Digital Input 29 OE Input Digital Enable (Active Low) to Tristate Output Data Pins. Digital Outputs 26 D7+ (MSB) Output Channel A/Channel B LVDS Output Data 7—True. 25 D7− (MSB) Output Channel A/Channel B LVDS Output Data 7—Complement. 24 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 23 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 22 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 21 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 20 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 19 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. Rev. A | Page 8 of 24 Document Outline Features Applications General Description Product Highlights Functional Block Diagram Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications SPI Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Voltage Reference RBIAS Clock Input Considerations Clock Input Options Digital Outputs Digital Output Enable Function () Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide