Datasheet AD9284 (Analog Devices) - 7

Data Sheet AD9284 ABSOLUTE MAXIMUM RATINGS Table 6.
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress Electrical rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −2.0 V to +2.0 V device reliability. D0+/D0− through D7+/D7− −0.3 V to DRVDD + 0.3 V to DRGND
THERMAL RESISTANCE
DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.3 V θJA is specified for the worst-case conditions, that is, a device CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V soldered in a circuit board for surface-mount packages. VIN±A, VIN±B to AGND −0.3 V to AVDD + 0.2 V SDIO/PWDN to DRGND −0.3 V to DRVDD + 0.3 V
Table 7. Thermal Resistance
CSB to AGND −0.3 V to DRVDD + 0.3 V
Package Type θJA θJC Unit
SCLK to AGND −0.3 V to DRVDD + 0.3 V 48-Lead LFCSP (CP-48-12) 30.4 2.9 °C/W Environmental Storage Temperature Range −65°C to +125°C
ESD CAUTION
Operating Temperature Range −40°C to +85°C Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. A | Page 7 of 24 Document Outline Features Applications General Description Product Highlights Functional Block Diagram Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications SPI Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Voltage Reference RBIAS Clock Input Considerations Clock Input Options Digital Outputs Digital Output Enable Function () Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide