Datasheet AD9286 (Analog Devices) - 9

Data Sheet AD9286 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6.
θ
Parameter Rating
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Electrical AVDD to AGND −0.3 V to +2.0 V
Table 7. Thermal Resistance
DRVDD to DRGND −0.3 V to +2.0 V
Package Type θJA θJC Unit
AGND to DRGND −0.3 V to +0.3 V 48-Lead LFCSP (CP-48-12) 30.4 2.9 °C/W AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− through D7+/D7− −0.3 V to DRVDD + 0.3 V to DRGND
ESD CAUTION
DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.3 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V AUXCLK+, AUXCLK− to AGND −0.3 V to AVDD + 0.2 V VIN1±, VIN2± to AGND −0.3 V to AVDD + 0.2 V SDIO/PWDN to DRGND −0.3 V to DRVDD + 0.3 V CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK to AGND −0.3 V to DRVDD + 0.3 V Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 9 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations VOLTAGE REFERENCE RBIAS CLOCK INPUT CONSIDERATIONS Clock Input Options Clocking Modes Interleave Performance DIGITAL OUTPUTS Digital Output Enable Function () BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE