Datasheet AD9286 (Analog Devices) - 3

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Data Sheet AD9286 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, unless otherwise noted.
Table 1. Parameter1 Temperature Min Typ Max Unit
RESOLUTION Full 8 Bits DC ACCURACY Differential Nonlinearity Full ±0.2 ±0.4 LSB Integral Nonlinearity Full ±0.1 ±0.3 LSB No Missing Codes Full Guaranteed Offset Error Full 0 ±0.4 ±2.1 % FS Gain Error Full 0 ±2 ±2.8 % FS MATCHING CHARACTERISTICS Offset Error2 Full 0 ±0.4 ±2.1 % FS Gain Error Full 0 ±0.05 ±0.2 % FS TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±20 ppm/°C ANALOG INPUT Input Span Full 1.2 V p-p Input Common-Mode Voltage Full 1.4 V Input Resistance (Differential) Full 16 kΩ Input Capacitance (Differential) Full 250 fF Full Power Bandwidth Full 700 MHz VOLTAGE REFERENCE Internal Reference Full 0.97 1 1.03 V Input Resistance Full 3 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current IAVDD Full 125 130 mA IDRVDD Full 51 54 mA POWER CONSUMPTION Sine Wave Input3 Full 315 330 mW Power-Down Power Full 0.3 1.7 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 See the Interleave Performance section. 3 Measured with a low frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Rev. C | Page 3 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations VOLTAGE REFERENCE RBIAS CLOCK INPUT CONSIDERATIONS Clock Input Options Clocking Modes Interleave Performance DIGITAL OUTPUTS Digital Output Enable Function () BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE