Datasheet AD9286 (Analog Devices)

8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter (ADC) Data Sheet AD9286 FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation
The AD9286 is an 8-bit, monolithic sampling, analog-to-digital
SNR: 49.3 dBFS at 200 MHz input at 500 MSPS
converter (ADC) that supports interleaved operation and is
SFDR: 65 dBc at 200 MHz input at 500 MSPS
optimized for low cost, low power, and ease of use. Each ADC
Low power: 315 mW at 500 MSPS
operates at up to a 250 MSPS conversion rate with outstanding
On-chip interleaved clocking
dynamic performance.
On-chip reference and track-and-hold
The AD9286 takes a single sample clock and, with an on-chip
1.2 V p-p analog input range for each channel
clock divider, time interleaves the two ADC cores (each running
Differential input with 500 MHz bandwidth
at one-half the clock frequency) to achieve the rated 500 MSPS.
LVDS-compliant digital output
By using the SPI, the user can accurately adjust the timing of the
On-chip voltage reference and sample-and-hold circuit
sampling edge per ADC to minimize the image spur energy.
DNL: ±0.2 LSB Serial port control options
The ADC requires a single 1.8 V supply and an encode clock for
Interleaved clock timing adjustment
full performance operation. No external reference components
Offset binary, Gray code, or twos complement data format
are required for many applications. The digital outputs are LVDS
Optional clock duty cycle stabilizer
compatible.
Built-in selectable digital test pattern generation
The AD9286 is available in a Pb-free, 48-lead LFCSP that is
Pin-programmable power-down function
specified over the industrial temperature range of −40°C to +85°C.
Available in 48-lead LFCSP PRODUCT HIGHLIGHTS APPLICATIONS
1. Integrated 8-Bit, 500 MSPS ADC.
Battery-powered instruments
2. Single 1.8 V Supply Operation with LVDS Outputs.
Handheld scope meters
3. Power-Down Option Controlled via a Pin-Programmable
Low cost digital oscilloscopes
Setting.
OTS: video over fiber FUNCTIONAL BLOCK DIAGRAM SDIO/ PWDN CSB SCLK OE CLK+ SPI CLK– VIN1+ ADC VIN1– R E VCM FFE AV D7+ (MSB), D7– (MSB) UT U P E VREF REF DS ×1.5 RL V T B SELECT CLOCK UT L E U 1.0V MANAGEMENT O D0+ (LSB), D0– (LSB) TP VREF INT OU VIN2– ADC DCO DCO+ VIN2+ GENERATION DCO– AUXCLK– AUXCLK+ AD9286
001
RBIAS AUXCLKEN AGND AVDD DRVDD DRGND
09338- Figure 1.
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations VOLTAGE REFERENCE RBIAS CLOCK INPUT CONSIDERATIONS Clock Input Options Clocking Modes Interleave Performance DIGITAL OUTPUTS Digital Output Enable Function () BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE