Datasheet AD9213 (Analog Devices) - 6

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AD9213 Preliminary Technical Data Parameter Temperature1 Min Typ Max Unit
LOGIC OUTPUT (SDIO) Logic Compliance CMOS Voltage Logic 1 (IOH = 9.6 mA) Full V Logic 0 (IOL = 9.1 mA) Full V DIGITAL OUTPUTS (SERDOUT_P[x], SERDOUT_N[x]) Compliance Full CML Output Voltage Differential Full mV p-p Offset Full mV p-p Differential Return Loss (RLDIFF)2 70°C dB Common-Mode Return Loss (RLCM) 70°C dB Differential Termination Impedance 70°C 100 Ω RESET (RSTB) Voltage Logic 1 Full V Logic 0 Full V Input Resistance Full 77 kΩ Input Capacitance Full pF PWDN Logic Compliance CMOS Voltage Logic 1 Full V Logic 0 Full V Input Resistance Full 44 kΩ Input Capacitance Full pF 1 Full temperature range is −10°C to +115°C junction temperature (Tj). Startup at a junction temperature of −40°C is guaranteed.All temperatures are junction temperatures. 2 Differential and common-mode return loss measured from 100 MHz to 0.75 × baud rate.
SWITCHING SPECIFICATIONS
Nominal supply voltages, specified maximum sampling rate, internal reference, AIN = −1.0 dBFS.
Table 4. Parameter Test Conditions/Comments Temperature1 Min Typ Max Unit
CLOCK (CLK) Maximum Clock Rate Full 10.25 GSPS Minimum Clock Rate Full 2.5 GSPS Clock Pulse Width High Full % duty cycle Clock Pulse Width Low Full % duty cycle SYSREF (SYSREF±)2 Setup Time (tSU_SR) 70°C ps Hold Time (tH_SR) 70°C ps FAST DETECT OUTPUT (FD) Latency Full Clock cycles OUTPUT PARAMETERS (SERDOUT[x]±) Rise Time 70°C ps Fall Time 70°C ps Pipeline Latency 70°C Clock cycles SYNCB± Falling Edge to First K.28 Characters 70°C Multiframes CGS Phase K.28 Characters Duration 70°C Multiframes Differential Termination Resistance 70°C Ω Rev. PrG | Page 6 of 97 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9213-6G AD9213-10G EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Input Overvoltage Clamp VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Synthesis Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode and Sensor TMU ADC FAST DETECT FAST THRESHOLD DETECTION (FD) DIGITAL DOWNCONVERTER DDC GENERAL DESCRIPTION Frequency Translation Stage (Optional) Filtering Stage Gain Stage (Optional) Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION Variable IF Mode ZIF Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode Example Calculation NCO FTW/POW/MAW/MAB Coherent Mode Example Calculation NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Profile Select Timer Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization during Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS M2_HB7 Filter Description M2_HB6 Filter Description M2_HB5 Filter Description M2_HB4 Filter Description M2_HB3 Filter Description M2_HB2 Filter Description M2_HB1 Filter Description M1_TB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop SETTING UP THE AD9213 DIGITAL INTERFACE JESD204B Transport Layer Settings Serial Line Rates K Settings DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION SAMPLED SYSREF MODE AVERAGED SYSREF MODE TEST MODES JESD204B TEST MODES SERIAL PORT INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER TABLES Open and Reserved Locations Default Values Logic Levels SPI Soft Reset REGISTER DETAILS: SYSTEM CONTROL SIGNALS (SPI_ONLY_REGMAP) REGISTER DETAILS: (USER_CTRL) REGISTER DETAILS: (AD9213_CUST_SPI_REGMAP) REGISTER DETAILS: (MAIN_REGMAP) REGISTER DETAILS: JTX_QBF REGISTER REGISTER DETAILS: DIG_DP_REGMAP REGISTER DETAILS: (AD9213_CUST_REG) REGISTER DETAILS: LCPLL_28NM REGISTER REGISTER DETAILS: JESD204B REGISTER MAP FOR FOUR CHANNELS (JTX_28NM_16CH) APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS