Datasheet AD9213 (Analog Devices) - 10

AD9213 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9213 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A SERDOUT JGND JGND SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT JGND JGND _N[1] _N[0] _N[2] _N[4] _N[6] _N[8] _N[10] _N[12] _N[14] _N[15] B SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT _N[3] _P[3] _P[1] _P[0] _P[2] _P[4] _P[6] _P[8] _P[10] _P[12] _P[14] _P[15] _P[13] _N[13] C SERDOUT SERDOUT SERDOUT SERDOUT JGND JGND JGND JGND JGND JGND JGND JGND JGND JGND _N[5] _P[5] _P[11] _N[11] D SERDOUT SERDOUT SERDOUT SERDOUT RES_DNC JVTT JVTT JVDD JVDD JVDD JVDD JVTT JVTT JVDD2 _N[7] _P[7] _P[9] _N[9] E JGND JGND RES_DNC TIE_LOW DGND DGND DGND DGND DGND RES_DNC RES_DNC SVDD2 JGND JGND F SYNCINB SVDD2 RES_DNC DGND DGND DGND DVDD DVDD DGND DGND AVSSFS8 SCLK CSB SYSREF _P _N G SYNCINB TMU_ TMU_ SYSREF TDN DVDD DVDD DVDD DVDD DVDD DVDD AVDDFS8 SDIO AVSSFS8 _N REFP DVDD1 _P H TMU_ VSS_ VSS_ CLKVDD_ FD TDP AGND AGND AGND AGND AGND AGND TRIG_P TRIG_N REFN MOAT MOAT HF CLKVDD_ J VDD_NVG VDD_NVG AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD VCO_FINE AGND HF K VNEG_ CLKVDD_ AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND VCO_VCM CLK_N OUT LF L TMU_ VCO_ VSS_NVG VSS_NVG RVDD2 BVDD3 AGND AGND AGND AGND AGND AGND CLKVDD CLK_P AVDD2 COARSE _LF M GPIO[4] GPIO[2] GPIO[3] BVNN2 BVNN1 AGND VOID VOID AGND BVDD2 FVDD PLLVDD2 AGND AGND N VCO_ RSTB GPIO[1] VREF AGND BVNN1 AGND VOID VOID AGND BVDD2 PDWN AGND AGND VREG
005
P AGND GPIO[0] VCM AVNN1 BVNN1 AGND VIN_P VIN_N AGND BVDD2 AGND RES_DNC RES_DNC AGND
15030-
192-BALL BALL GRID ARRAY, THERMALLY ENHANCED [BGA_ED] (BP-192-1)
Figure 5. Pin Configuration, Top View, Not To Scale
Table 8. Pin Function Descriptions Pin No. Ball Name Input/Output Signal Type Description
P3 VCM Output Static Export VCM P7, P8 VIN_P, VIN_N Input RF ADC inputs, high frequency N3 VREF Input Static Optional VREF Import H3, G3 TDP, TDN Static Temperature Diode anode/cathode (can float if unused) L14, K14 CLK_P, CLK_N Input RF Clock inputs, high frequency G14, F14 SYSREF_P, SYSREF_N Input/output LVDS/CML Differential Synchronization Signal. Critical timing relative to CLK. Placed near CLK inputs. Used to establish deterministic latency. (Internally tied to ground through 50 Ω in default configuration. Can leave floating if set to Subclass0 mode by Register 0x525) H13, H14 TRIG_P, TRIG_N Input LVDS Trigger input for freq. hopping. Similar to SYSREF inputs. (Internally tied to ground through 50 Ω in default configuration. Can leave floating if left disabled by default with Register 0x602) K12 VCO_VCM Input/output Static PLL: Common-mode pin tapping from center of VCO, used in filter J12 VCO_FINE Input/output Static PLL loop filter fine connection Rev. PrG | Page 10 of 97 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9213-6G AD9213-10G EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Input Overvoltage Clamp VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Synthesis Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode and Sensor TMU ADC FAST DETECT FAST THRESHOLD DETECTION (FD) DIGITAL DOWNCONVERTER DDC GENERAL DESCRIPTION Frequency Translation Stage (Optional) Filtering Stage Gain Stage (Optional) Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION Variable IF Mode ZIF Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode Example Calculation NCO FTW/POW/MAW/MAB Coherent Mode Example Calculation NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Profile Select Timer Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization during Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS M2_HB7 Filter Description M2_HB6 Filter Description M2_HB5 Filter Description M2_HB4 Filter Description M2_HB3 Filter Description M2_HB2 Filter Description M2_HB1 Filter Description M1_TB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop SETTING UP THE AD9213 DIGITAL INTERFACE JESD204B Transport Layer Settings Serial Line Rates K Settings DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION SAMPLED SYSREF MODE AVERAGED SYSREF MODE TEST MODES JESD204B TEST MODES SERIAL PORT INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER TABLES Open and Reserved Locations Default Values Logic Levels SPI Soft Reset REGISTER DETAILS: SYSTEM CONTROL SIGNALS (SPI_ONLY_REGMAP) REGISTER DETAILS: (USER_CTRL) REGISTER DETAILS: (AD9213_CUST_SPI_REGMAP) REGISTER DETAILS: (MAIN_REGMAP) REGISTER DETAILS: JTX_QBF REGISTER REGISTER DETAILS: DIG_DP_REGMAP REGISTER DETAILS: (AD9213_CUST_REG) REGISTER DETAILS: LCPLL_28NM REGISTER REGISTER DETAILS: JESD204B REGISTER MAP FOR FOUR CHANNELS (JTX_28NM_16CH) APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS