Datasheet AD7813 (Analog Devices) - 7

AD7813 CIRCUIT DESCRIPTION SUPPLY Converter Operation 2.7V TO 5.5V 10 F 0.1 F
The AD7813 is a successive approximation analog-to-digital
PARALLEL
converter based around a charge redistribution DAC. The ADC
VDD VREF INTERFACE
can convert analog input signals in the range 0 V to VDD. Fig-
DB0-DB7
ures 2 and 3 below show simplified schematics of the ADC.
AD7813
Figure 2 shows the ADC during its acquisition phase. SW2 is
0V TO VREF BUSY VIN INPUT C/ P
closed and SW1 is in Position A, the comparator is held in a
RD
balanced condition and the sampling capacitor acquires the
GND CS
signal on VIN+.
CONVST CHARGE REDISTRIBUTION
Figure 4. Typical Connection Diagram
DAC SAMPLING Analog Input CAPACITOR A V
Figure 5 shows an equivalent circuit of the analog input struc-
IN+ CONTROL SW1 LOGIC
ture of the AD7813. The two diodes, D1 and D2, provide ESD
B ACQUISITION SW2
protection for the analog inputs. Care must be taken to ensure
PHASE COMPARATOR
that the analog input signal never exceeds the supply rails by
CLOCK AGND VDD/3
more than 200 mV. This will cause these diodes to become
OSC
forward biased and start conducting current into the substrate. Figure 2. ADC Track Phase The maximum current these diodes can conduct without caus- ing irreversible damage to the part is 20 mA. The capacitor C2, When the ADC starts a conversion (see Figure 3), SW2 will in Figure 5, is typically about 4 pF and can be primarily attrib- open and SW1 will move to Position B, causing the comparator uted to pin capacitance. The resistor R1 is a lumped component to become unbalanced. The Control Logic and the Charge made up of the on resistance of a multiplexer and a switch. This Redistribution DAC are used to add and subtract fixed amounts resistor is typically about 125 Ω. The capacitor C1 is the ADC of charge from the sampling capacitor so as to bring the compara- sampling capacitor and has a capacitance of 3.5 pF. tor back into a balanced condition. When the comparator is rebalanced the conversion is complete. The Control Logic gen-
VDD
erates the ADC output code. Figure 7 shows the ADC transfer function.
D1 R1 C1 125 3.5pF V V CHARGE IN DD/3 REDISTRIBUTION C2 CONVERT PHASE – SWITCH OPEN DAC D2 4pF TRACK PHASE – SWITCH CLOSED SAMPLING CAPACITOR A VIN+ CONTROL SW1 LOGIC SW2 B CONVERSION
Figure 5. Equivalent Analog Input Circuit
PHASE COMPARATOR DC Acquisition Time CLOCK AGND VDD/3 OSC
The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the Figure 3. ADC Conversion Phase end of a conversion there is a settling time associated with the sampling circuit. This settling time lasts approximately 100 ns.
TYPICAL CONNECTION DIAGRAM
The analog signal on VIN is also being acquired during this settling Figure 4 shows a typical connection diagram for the AD7813. The time; therefore, the minimum acquisition time needed is parallel interface is implemented using an 8-bit data bus, the approximately 100 ns. falling edge of CONVST brings the BUSY signal high, and at Figure 6 shows the equivalent charging circuit for the sampling the end of conversion the falling edge of BUSY is used to ini- capacitor when the ADC is in its acquisition phase. R2 repre- tiate an Interrupt Service Routine (ISR) on a microprocessor— sents the source impedance of a buffer amplifier or resistive see Parallel Interface section for more details. VREF is connected network, R1 is an internal multiplexer resistance and C1 is the to a well decoupled VDD pin to provide an analog input range of sampling capacitor. 0 V to VDD. When VDD is first connected the AD7813 powers up in a low current mode, i.e., power-down. A rising edge on an
R1
internal CONVST input will cause the part to power up—see
V R2 IN 125
Power-Up Times. If power consumption is of concern, the automatic power-down at the end of a conversion should be
C1 3.5pF
used to improve power performance. See Power vs. Throughput Rate section of the data sheet. Figure 6. Equivalent Sampling Circuit –6– REV. C