Datasheet AD7813 (Analog Devices) - 9

AD7813 Typical Performance Characteristics
At the end of conversion the sampling circuit goes back into its tracking mode again. The end of conversion is indicated by the BUSY signal going low. This signal may be used to initiate an
10
ISR on a microprocessor. At this point the conversion result is latched into the output register where it may be read. The AD7813 has an 8-bit wide parallel interface. The 10-bit conversion result is accessed by performing two successive read operations. The
1
first 8-bit read accesses the 8 MSBs of the conversion result and the second read accesses the 2 LSBs, as illustrated in Figure 13,
mW –
where one performance of the two successive reads is highlighted after the falling edge of BUSY. The state of the external CONVST
POWER 0.1
signal at the end of conversion also establishes the mode of opera- tion of the AD7813.
Mode 1 Operation (High Speed Sampling)
If the external CONVST is logic high when BUSY goes low, the
0.01
part is said to be in Mode 1 operation. While operating in Mode
0 5 10 15 20 25 30 35 40 45 50 THROUGHPUT – kSPS
1, the AD7813 will not power down between conversions. The AD7813 should be operated in Mode 1 for high speed sampling Figure 10. Power vs. Throughput applications, i.e., throughputs greater than 100 kSPS. Figure 13 shows the timing for Mode 1 operation. From this diagram one
0 AD7813
can see that a minimum delay of the sum of the conversion time
–10 2048 POINT FFT
and read time must be left between two successive falling edges
SAMPLING 357.142kHz –20 fIN 30.168kHz
of the external CONVST. This is to ensure that a conversion is
–30
not initiated during a read.
–40 Mode 2 Operation (Automatic Power-Down) –50
At slower throughput rates the AD7813 may be powered down
dBs
between conversions to give a superior power performance.
–60
This is Mode 2 Operation and it is achieved by bringing the
–70
CONVST signal logic low before the falling edge of BUSY.
–80
Figure 14, overleaf, shows the timing for Mode 2 Operation.
–90
The falling edge of the external CONVST signal may occur before or after the falling edge of the internal CONVST signal,
–100 0 17 35 52 70 87 105 122 140 157 174
but it is the later occurring falling edge of both that controls
FREQUENCY – kHz
when the first conversion will take place. If the falling edge Figure 11. SNR of the external CONVST occurs after that of the internal CONVST, it means that the moment of the first conversion is
TIMING AND CONTROL
controlled exactly, regardless of any jitter associated with the The AD7813 has only one input for timing and control, i.e., internal CONVST signal. The parallel interface is still fully the CONVST (convert start signal). The rising edge of this operational while the AD7813 is powered down. The AD7813 CONVST signal initiates a 1.5 µs pulse on an internally gener- is powered up again on the rising edge of the CONVST signal. ated CONVST signal. This pulse is present to ensure the part The gated CONVST pulse will now remain high long enough has enough time to power up before a conversion is initiated. If for the AD7813 to fully power up, which takes about 1.5 µs. This the external CONVST signal is low, the falling edge of the is ensured by the internal CONVST signal, which will remain high internal CONVST signal will cause the sampling circuit to go for 1.5 µs. into hold mode and initiate a conversion. If, however, the exter- nal CONVST signal is high when the internal CONVST goes low, it is upon the falling edge of the external CONVST signal
EXT CONVST
that the sampling circuitry will go into hold mode and initiate a
(PIN 4) GATED
conversion. The use of the internally generated 1.5 µs pulse,
INT
as previously described, can be likened to the configuration shown in Figure 12. The application of a CONVST signal at
1.5 s
the CONVST pin triggers the generation of a 1.5 µs pulse. Both the external CONVST and this internal CONVST are input to Figure 12. an OR gate. The resulting signal has the duration of the longer of the two input signals. Once a conversion has been initiated the BUSY signal goes high to indicate a conversion is in progress. –8– REV. C