Datasheet AD7655 (Analog Devices) - 9

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AD7655 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ND A B G ND ND F F F F AGND AGND INA1 INAN INA2 REFA REFB INB2 INBN INB1 REFGND REF AG AG INA1 INAN INA2 RE RE INB2 INBN INB1 RE RE 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 DVDD AGND 1 36 DVDD PIN 1 AVDD 2 35 CNVST AVDD 2 35 CNVST A0 3 34 PD A0 3 34 PD BYTESWAP 4 33 RESET BYTESWAP 4 33 RESET A/B 5 32 CS DGND 6 AD7655 31 RD A/B 5 32 CS TOP VIEW AD7655 IMPULSE 7 30 EOC (Not to Scale) DGND 6 31 SER/PAR TOP VIEW RD 8 29 BUSY D0 9 28 D15 IMPULSE 7 (Not to Scale) 30 EOC D1 10 27 D14 SER/PAR 8 29 BUSY D2/DIVSCLK[0] 11 26 D13 D3/DIVSCLK[1] 12 25 D12 D0 9 28 D15 D1 10 27 D14 13 14 15 16 17 18 19 20 21 22 23 24 D2/DIVSCLK[0] 11 26 D13 T K N D K R NC DI DD DD ND UT NC D3/DIVSCLK[1] 12 25 D12 Y CL V CL Y T/IN S S S X OGN O DV DG DO S S RRO S 13 14 15 16 17 18 19 20 21 22 23 24 /E INV INV D9/ 4 RDC/ D8/ D10/ RDE D D5/ D6/ D7/ D11/ OGND OVDD DVDD DGND NOTES D9/SCLK
035
D10/SYNC 1. THE EPAD IS CONNECTED TO GROUND; HOWEVER, THIS CONNECTION D4/EXT/INT D8/SDOUT D5/INVSYNC D6/INVSCLK IS NOT REQUIRED TO MEET SPECIFIED PERFORMANCE. D7/RDC/SDIN
03536-
D11/RDERROR
03536-004 Figure 4. 48-Lead LQFP Pin Configuration Figure 5. 48-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 47, 48 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 5 V. 3 A0 DI Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted. 4 BYTESWAP DI Parallel Mode Selection (8 Bit, 16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 A/B DI Data Channel Selection. In parallel mode, when LOW, the data from Channel B is read. When HIGH, the data from Channel A is read. In serial mode, when HIGH, Channel A is output first followed by Channel B. When LOW, Channel B is output first followed by Channel A. 6, 20 DGND P Digital Power Ground. 7 IMPULSE DI Mode Selection. When HIGH, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the serial master read after convert mode. These inputs, part of the serial port, are used to slow down the internal serial clock that clocks the data output. In the other serial modes, these inputs are not used. 13 D[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock called, respectively, master and slave mode. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. Rev. E | Page 8 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION CIRCUIT INFORMATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS INPUT CHANNEL MULTIPLEXER DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) Channel A/ Output SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Convert External Clock Data Read (Previous) During Convert MICROPROCESSOR INTERFACING SPI INTERFACE (ADSP-2191M) APPLICATION HINTS LAYOUT EVALUATING THE AD7655 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE