Datasheet AD7655 (Analog Devices) - 8

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Data Sheet AD7655 ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses at or above those listed under Absolute Maximum
Parameter Value
Ratings may cause permanent damage to the product. This is a Analog Input stress rating only; functional operation of the product at these INAx1, INBx1, REFx, INxN, REFGND AVDD + 0.3 V to or any other conditions above those indicated in the operational AGND − 0.3 V section of this specification is not implied. Operation beyond Ground Voltage Differences the maximum operating conditions for extended periods may AGND, DGND, OGND ±0.3 V affect product reliability. Supply Voltages AVDD, DVDD, OVDD –0.3 V to +7 V
1.6mA IOL
AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD −0.3 V to +7 V
TO OUTPUT 1.4V
Digital Inputs −0.3 V to DVDD + 0.3 V
PIN CL 60pF*
Internal Power Dissipation2 700 mW Internal Power Dissipation3 2.5 W
500
µ
A IOH
Junction Temperature 150°C
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
Storage Temperature Range −65°C to +150°C
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C
Lead Temperature Range
L OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
03536-002 (Soldering 10 sec) 300°C Figure 2. Load Circuit for Digital Interface Timing 1 See the Analog Inputs section.
2V
2 Specification is for device in free air: 48-lead LQFP, θ
0.8V
JA = 91°C/W, θJC = 30°C/W.
tDELAY tDELAY
3 Specification is for device in free air: 48-lead LFCSP, θJA = 26°C/W.
2V 2V 0.8V 0.8V
03536-003 Figure 3. Voltage Reference Levels for Timing
ESD CAUTION
Rev. E | Page 7 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION CIRCUIT INFORMATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS INPUT CHANNEL MULTIPLEXER DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) Channel A/ Output SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Convert External Clock Data Read (Previous) During Convert MICROPROCESSOR INTERFACING SPI INTERFACE (ADSP-2191M) APPLICATION HINTS LAYOUT EVALUATING THE AD7655 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE