Datasheet AD9255 (Analog Devices) - 6

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Data Sheet AD9255 ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 2. AD9255BCPZ-802 AD92 55BCPZ-1052 AD92 55BCPZ-1252 Parameter1 T emp Min Typ Max Min Typ Max Min Typ Ma Unit x
SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz 25°C 79.2 78.9 78.3 dBFS fIN = 70 MHz 25°C 78.9 78.5 78.3 dBFS Full 78.1 77.6 76.9 dBFS fIN = 140 MHz 25°C 78.0 77.7 77.1 dBFS fIN = 200 MHz 25°C 76.9 76.4 75.5 dBFS SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 2.4 MHz 25°C 78.7 78.6 78.0 dBFS fIN = 70 MHz 25°C 78.7 78.0 78.0 dBFS Full 77.9 77.3 76.7 dBFS fIN = 140 MHz 25°C 76.8 77.0 76.7 dBFS fIN = 200 MHz 25°C 75.8 75.3 74.3 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz 25°C 12.8 12.8 12.7 Bits fIN = 70 MHz 25°C 12.8 12.7 12.7 Bits fIN = 140 MHz 25°C 12.5 12.5 12.4 Bits fIN = 200 MHz 25°C 12.3 12.2 12.0 Bits WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz 25°C −88 −90 −88 dBc fIN = 70 MHz 25°C −94 −89 −93 dBc Full −91 −88 −85 dBc fIN = 140 MHz 25°C −82 −86 −89 dBc fIN = 200 MHz 25°C −81 −81 −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz 25°C 88 90 88 dBc fIN = 70 MHz 25°C 94 89 93 dBc Full 91 88 85 dBc fIN = 140 MHz 25°C 82 86 89 dBc fIN = 200 MHz 25°C 81 81 80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) Without Dither (AIN at −23 dBFS) fIN = 2.4 MHz 25°C 102 99 96 dBFS fIN = 70 MHz 25°C 103 97 99 dBFS fIN = 140 MHz 25°C 104 97 98 dBFS fIN = 200 MHz 25°C 102 101 97 dBFS With On-Chip Dither (AIN at −23 dBFS) fIN = 2.4 MHz 25°C 110 109 108 dBFS fIN = 70 MHz 25°C 110 108 109 dBFS fIN = 140 MHz 25°C 110 108 109 dBFS fIN = 200 MHz 25°C 110 109 109 dBFS Rev. C | Page 5 of 44 Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide