Datasheet AD9255 (Analog Devices)

14-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9255 FEATURES APPLICATIONS SNR = 78.3 dBFS at 70 MHz and 125 MSPS Communications SFDR = 93 dBc at 70 MHz and 125 MSPS Multimode digital receivers (3G) Low power: 371 mW at 125 MSPS GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and 1.8 V analog supply operation TD-SCDMA 1.8 V CMOS or LVDS output supply Smart antenna systems Integer 1-to-8 input clock divider General-purpose software radios IF sampling frequencies to 300 MHz Broadband data applications −153.4 dBm/Hz small signal input noise with 200 Ω input Ultrasound equipment impedance at 70 MHz and 125 MSPS PRODUCT HIGHLIGHTS Optional on-chip dither Programmable internal ADC voltage reference
1. On-chip dither option for improved SFDR performance
Integrated ADC sample-and-hold inputs
with low power analog input.
Flexible analog input range: 1 V p-p to 2 V p-p
2. Proprietary differential input that maintains excellent SNR
Differential analog inputs with 650 MHz bandwidth
performance for input frequencies up to 300 MHz.
ADC clock duty cycle stabilizer
3. Operation from a single 1.8 V supply and a separate digital
Serial port control
output driver supply accommodating 1.8 V CMOS or
User-configurable, built-in self-test (BIST) capability
LVDS outputs.
Energy-saving power-down modes
4. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. 5. Pin compatibility with the AD9265, allowing a simple migration up to 16 bits.
FUNCTIONAL BLOCK DIAGRAM SENSE RBIAS PDWN AGND AVDD (1.8V) LVDS LVDS_RS REFERENCE VREF AD9255 VCM DRVDD (1.8V) VIN+ TRACK-AND-HOLD VIN– OUTPUT ADC 14 STAGING 14 DITHER 14-BIT CMOS OR D13 TO D0 CORE LVDS (DDR) CLK+ CLOCK OR CLK– MANAGEMENT OEB SYNC SERIAL PORT DCO
001
SVDD SCLK/ SDIO/ CSB DFS DCS
08505- Figure 1.
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Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide